Enterprise Product Unit
RF Engineer
1. RF development, design review and progress control of Netcom Product
2. Guide RF testing, verification and debugging
3. Discuss product RF specifications and development details with customers in English
4. Lead the R&D team members to jointly achieve the project objectives
5. Cross-departmental communication, coordination and cooperation
1. 針對高速介面進行信號完整性模擬。
SI simulation : TDR, S parameter,Eye diagram,Crosstalk..
2. 電路板電源完整性模擬。
PI simulation : IR Drop , PDN..
3. 對於佈局圖給予改良建議。
Polar應用及評估PCB & VNA材料選擇方式
4. 信號完整性異常除錯。
PRF 技術員將負責支援 RF/PRF 製造工具、機台及製程。他們的工作內容包括審查與分析各種製造中出現的問題,例如產品規格不符、設備維修需求、預防性維護、設備認證、設備管理、作業指導書等。此外,他們也將與工程團隊密切合作,協助故障排除、新設備與製程的測試與調校,以及生產支援等相關工作。
Responsibilities:
1. Must be able to work in the 2nd-shift timeframe (22:00~7:00) on a daily basis.
須於大夜班時段(22:00~7:00)執行工作。
2. Program/setup/troubleshoot equipment including cable prep machine, induction soldering, electrical testers and PNA(Anduin).
生產及測試設備之程式指令設定、架設、故障排除,例如裁切線設備、高週波感應加熱、電測機、PNA系統等。
3. Utilize Solution Center Tools Level 1 to communicate manufacturing issues that cannot be resolved on the production floor.
依照工作標準流程協助產線進行生產問題之初步處理。
4. Responsible for debugging, maintaining, repairing and keeping in working order all production tooling and machine on daily basis.
負責日常生產治具及設備之問題排除、保養、檢修,確保可正常使用。
5. Ensure all tooling and machine is up to date states for ISO reference or audit.
確認治具及產線設備均符合最新使用規定,符合ISO稽核要求。
6. Ensure tooling and machine PM is performed accordingly.
確保按時完成治具及設備之預防性維護作業。
7. Maintain and replenish spare parts for tooling and machine.
治具及設備之備品物料之維護與補充等管理。
8. To support or troubleshoot production tooling or machine breakdown.
支援或排除生產治具與設備之故障。
9. To liaise with other facilities on new tooling & new machine for new project that transferred to Samtec Taiwan.
與其他廠區窗口接洽、確認新轉移至台灣廠之治具與設備。
10. Identify and implement improvements tooling and machine.
辨識及執行治具與設備之改善作業。
11. Assemble and debug new tooling.
組裝及排除新治具之問題。
12. Other relevant tooling and machine function as requested by Management.
其他相關治具與設備等主管交辦事項。
13. Any other job related duties as assigned by management.
其他與職責相關之主管交辦事項。
14. Adheres to all Samtec Quality Principles and actions.
須遵守所有Samtec品質規定。
“The responsibilities as defined are intended to serve as a general guideline for this position. Associates may be asked to perform additional tasks depending on strengths and capabilities.”
THE ROLE
The Lead Signal Integrity Engineer is a technical leader responsible for advancing Isola’s laminate materials to meet and exceed high-speed electrical and signal integrity (SI) performance requirements. This role provides mentorship and direction to the Signal Integrity team in Taiwan, drives innovation in SI test methodologies, and ensures strong technical engagement with global OEMs. The Lead serves as a recognized authority in SI, bridging customer needs with material performance and representing Isola in the high-performance electronics community.
KEY RESPONSIBILITIES:
Customer-Facing Technical Support:
• Lead technical engagement with OEMs and direct customers on high-speed laminate characterization.
• Act as primary technical contact for SI-related design validation and adoption cycles.
• Oversee the creation of technical reports, white papers, and collateral for internal and external use.
Strategic & Technical Leadership:
• Define and develop advanced SI measurement, modeling, and simulation methodologies.
• Collaborate with Product Management, R&D, and Sales to ensure alignment of SI capabilities with product strategy.
• Represent Isola as a thought leader through publications, conferences, and industry forums.
Organizational Management:
• Mentor, guide, and grow the Taiwan-based Signal Integrity Engineering team.
• Establish scalable, cost-effective SI test methods that accelerate R&D and customer response.
• Drive alignment with global Application Engineering teams to ensure best-in-class technical service.
Technology & Standards Thought Leadership:
• Maintain expertise in SI methods, PCB processing effects, and high-speed digital design requirements.
• Contribute to industry standards development and support customer forums on SI requirements.
QUALIFICATIONS & EXPERIENCE
• 8+ years of experience in signal integrity engineering, PCB laminates, or high-speed design.
• Expertise in VNA measurements, probing techniques, and advanced SI methodologies.
• Experience with PCB manufacturing and processing effects on SI performance.
• Demonstrated leadership and mentoring experience.
• Proven record of technical publications, white papers, or conference presentations.
EDUCATION
• PhD or Master’s in Electrical Engineering or related field required.
OTHER CONSIDERATIONS
• Fluent in English – required for global communication and technical documentation.
• Proficiency in Mandarin Chinese – strongly preferred for engagement with Taiwan/China teams and customers.
• Ability to travel regionally and globally as needed.
1. 1. High-speed I/O interface and product design
2. Signal integrity (SI) simulation for a high-speed interface such as PCIe Gen4/Gen5, DDR4/DDR5 memory, IEEE 802.3 Ethernet 100G/400G/800G, etc.
3. Power Integrity (PI) simulation on ASIC or FPGA-based systems, perform design analysis such as DC IR-drop/AC PDN impedance, and De-cap optimization to ensure system performance.
4. Lab measurement knowledge and skills for SI&PI correlation.
5. Co-work with the H/W designer (EE) to define specifications and solve the related signal problems in the system
6. Provide PCB layout guidelines and perform the layout/design review with EE and the layout team during the design stage.