「Substrate Layout 工程」的相似工作

- Job Description - Responsible for assisting in project documentation, layout planning, and follow-up tasks, supporting substrate layout design for advanced probe cards. - Responsibilities - • Organize project documents and design data • Plan and execute substrate layout drawings • Perform design checks (DRC, DFM) • Collaborate with manufacturing teams to meet design requirements and implement changes • Support CAM data verification and output before manufacturing - Qualifications - • No specific experience required; interest in PCB/substrate layout is a plus • Related layout experience preferred; training will be provided for new graduates • Familiarity with Cadence Allegro is a strong plus • Familiarity with Cam350 is a plus - Preferred Skills - • Understanding of PCB/substrate design workflow • Experience in high-speed signal or power routing • Background in packaging or probe card industry

1.鋰電池BMS電路layout設計 2.確認電路PCB及FPC layout 3.開發新的軟性PCB及高速PCB的驅動板 4.相關layout文件處理 5.協助處理其他產品設計相關事宜 6.配合電子及機構工程師作業及主管交辦事項

1. Flip chip package substrate design. 2. Capable provide optimization design proposal. 3. Capable to co-work with substrate/material suppliers directly. 4. Design rule maintenance. 5. Work closely and Interface with various teams (product, PE group and supplier…etc) 6. A plus for Good command of written and oral in English.

(1)Probe Card MLO/Carrier載板案件製造評估。 (2)與製造單位溝通廠內DFM(製程能力表)。 (3)疊構設計評估。 (4)BGA Pin Definition評估 (5)高速訊號/一般IO/電源 Layout Routing (6)BOM及Gerber產出。 *無經驗可(有MLO/載板設計經驗或有濃厚興趣者尤佳)。 *有Allegro Orcad/PCB Designer/APD+/CAM軟體操作經驗一年以上者優先面談。 *有PISI模擬經驗者優先面談 *細心沉穩、配合度高、情緒管理能力好、學習意願高者尤佳。 日班 08:30-17:30/中班 13:00-21:30 班別可選擇

CP / FT / BIB PCB Layout 佈線、佈排

1.PCB Layout design, 須專精Allegro軟體 2.熟悉burn in board PCB設計 3.客戶技術溝通協調 4.產出PCB生產文件，建立並維護元器件的零件庫 4.視工作表現而定，額外提供每月點數獎金 5.表現優秀，培養二年後年薪可破百萬

1. 具Load board / Probe card 設計經驗者擇優 2. 零件Library 建立 3. 相關設計表單整理與輸出

IC layout

1.Layuot設計，PCB發包製作，SMT/DIP發包製作。 2.研究製作PCB產品相關分析與報告。 3.協助技術文件編寫。 Job Description 1.Layout design, PCB outsourcing and production, SMT/DIP outsourcing and production. 2.Research and create analyses and reports related to PCB product manufacturing. 3.Assist in the preparation of technical documents.

1.SENSOR-LAYOUT、設計作業 2.產品開發及修改，進度管控、設計改善 3.與供應商技術溝通、時程管控、改善分析 4.其他主管交辦任務

1. Analog mixed signal IC layout 2. 熟悉IC Layout tool 3. 熟悉先進製程

1. PCB佈局、擺件、佈線 2. Design Rule & Allegro Constraint 設定 3. CAD/CAM檢查與Gerber輸出 4. 協助解決PCB設計、PCB製造及PCB組裝的各項工程問題

Layout Design 協助專案佈線,文字面等後續處理事宜

1.產品高頻特性測試 2.產品高頻FAE 及FA特性分析 3.測試設備開發及PCB設計製作/驗收 4.專案開發人員

1.Analog and mixed mode circuit layout and verification 2.Co-work with designer for layout floor planning,routing and physical verifications 3.command file maintain

1. Probe Card PCB Layout 2. 確認產品需求/設計 3. 協助客戶完成PCB設計 4. 廠內外溝通，完成主管交辦事項

1.CIS/3DIC/HBM & RDL package layout. (follow customer design) 2.Daisy chain design 3.Wafer 排版評估及圖面製作 4.光罩排版設計 5.Job file資料提供及其它生產相關圖面製作.(POD drawing, Mask drawing, Unit drawing Other Job Function 1.Check Mask Design SOP (L-EDIT ). 2.Design review meeting. 3.Review and maintain for relevant document ＊實際薪資依學歷、科系、相關工作經驗、專業證照、特殊專長與語言能力綜合核敘。 ＊資深人員薪資另議。

【工作內容】 • 我們正在尋找具備先進製程經驗的 IC Layout 工程師，加入團隊後可以參與高階SoC /Analog IP 的實體實現，並負責以下工作： -Mixed-Mode FinFET Layout 設計與繪製，確保電路佈局在效能、面積與可靠性之間取得最佳平衡。 -進行 FinFET 製程相關的 DRC / LVS / ERC 驗證，確保設計符合法規與 Foundry 要求。 -熟悉 XRC & EM/IR 分析流程，進行可靠性評估，並針對潛在問題提出改善方案。 【職務條件】 • 必備條件：具備 FinFET 製程經驗，能獨立進行版圖設計與驗證。 -具備類比電路佈局經驗，了解電路特性與佈局考量，能與設計工程師密切合作。 -具備良好的溝通能力與團隊合作精神，能在專案時程內交付高品質成果。

1. Ensure PKG design is optimized with SI/PI/Thermal requirements. 2. Create the PKG/RDL/Subtract SI 3D modeling and perform extraction of S-Parameters and RLGC model. 3. Full-wave modeling of VIAs, Connectors, Package and PCB channels, components using 3D full-wave EM tools. 4. Provide the CM(Construction rules) and Design Rules(guidelines) for the PKG/RDL/Subtract design. 5. Provide the Substrate manufacturing process and material property. 6. SI(Signal integrity) simulation and optimization on package stack-up, power/ ground plane assignment and optimization, decoupling cap locations to minimize power ground noise. 7. PI(Power integrity) analysis for state of art package/system designs, which include but not limited to package layout model extraction, transient noise analysis to meet the silicon noise spec, decoupling strategy and analysis. 8. CTK(Crosstalk) analysis and reduction on-package considering mutual-effect by on-die, on-silicon interposer and on-PCB. 9. SSN(Simultaneous Switching Noise)/SSO analysis for I/O (DDR5/4/3, LPDDR5/4/3, etc.) power domain. 10. Eye diagram(ZRZ/PAM4) and jitter analysis for CPS(Die Chip-PKG-System PCB) co-simulations. 11. Familiar with trade-offs among package cost, technologies, design, performance, power, and thermal requirements. 12. Familiar with assembly and substrate manufacturing process is a plus. 13. Familiar with programming/scripting in Java, VBScript, PERL, TCL, MatLab and/or equivalent. 14. Experienced in SI PI automation tool development with Python or PyAEDT is a plus. 15. Working with ASIC/HW/Production team.

1. 熟悉allegro 或PADS Layout 軟體 , 有PCB Layout 3年以上的經驗尤佳. 2. 善於溝通協調及控制LAYOUT的品質及SCHEDULE.