1. MSEE is required.
2. Solid background in analog integrated circuits.
3. Knowledge of high speed serial link technology.
4. Familiar with SerDes PHY (USB, PCIE Express, SATA and Thunderbolt) and building block (DFE, CTLE, CDR, PLL and FFE transmitter).
5. Experience in design and simulation high speed transceiver is a plus.
Job desicription:
Our Design Team specializes in the challenging field of Non-Volatile Memory (NVM) IC circuit design. We are actively seeking an experienced Analog Circuit Design Engineer to contribute to our cutting-edge developments in embedded NVM solutions and surrounding circuitry.
As a key member of our team, you will be responsible for the design, verification, and debugging of essential analog building blocks like Bandgap references, LDOs, and Charge Pumps. A significant part of your role will involve designing critical memory peripheral circuits for NVM IP and test chips, including Array interfaces, Decoding logic, and Sense Amplifiers.
Your responsibilities will span the design lifecycle, from contributing to IP specifications and core circuit design to ensuring performance through layout optimization and comprehensive corner simulations of NVM IPs. We are looking for candidates with proven expertise in analog circuit design, ideally with prior experience in embedded memory or NVM technologies.
If you are an experienced analog designer eager to tackle complex challenges in non-volatile memory, we encourage you to apply and help shape the future of memory technology.
Digital IC design engineer
- Familiar with Verilog RTL coding
- Familiar with digital design flow (pre-layout simulation, timing constraint, synthesis, post-layout simulation)
- Will be working on high speed Serdes IPs
- Experience or interest in all-digital PLLs or clock-data recovery circuits is a big plus
1. Main responsibility is to design analog IPs in MCU such as adc/dac, pll, osc, por, ldo
2. 具備DC-DC Converter, Buck相關電路設計
2. Responsible for analog IP design, verification plan, test plan, document
3. Communicate with system, layout and digital engineer to ensure high quality
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雅特力科技創立於2016年,為智原科技子公司。
【Artery雅特力】即將在台上市的IC設計公司,主要產品為32bit ARM core base MCU
公司網址:https://www.arterychip.com
關於雅特力:https://www.104.com.tw/company/1a2x6blojm
We are seeking a skilled Analog IC Design Engineer with expertise in MIPI TX/ PLL design and sensor readout circuits. The ideal candidate will possess a strong foundation in analog design and a passion for developing cutting-edge solutions in a collaborative environment.
1.Design and implement MIPI TX and PLL circuits for high-speed data transmission.
2.Develop charge pump and LDO (Low Dropout Regulator) circuits to ensure efficient power management.
3.Design and optimize oscillator (OSC) circuits for precise timing applications.
4.Create sensor readout circuits, including CDS (Correlated Double Sampling), TDC (Time-to-Digital Converter), ramp circuits, DAC (Digital-to-Analog Converter), and comparators.
5.Collaborate with system engineers to define specifications and ensure alignment with overall project requirements.
6.Perform circuit simulations and analyses using tools such as Cadence, Spectre, or HSPICE.
7.Conduct design verification and validation through prototyping and testing.
8.Optimize designs for performance, power efficiency, and reliability.
9.Participate in design reviews and contribute to project documentation.
10.Provide support during the layout and fabrication process.
Preferred Qualifications:
1.Familiarity with IP design principles.
2.Experience with mixed-signal circuits.
3.Knowledge of low-noise and high-speed design techniques.
We are currently seeking a talented Analog Design Engineer to join our team and participate in the development of Power IC for High-Performance Computing (HPC). The role will primarily involve working on the design and development of the following components:
1. PMIC (Power Management Integrated Circuit)
2. Multiphase VR (Voltage Regulator)
3. Buck/Boost/Buck-Boost Converters
4. eFuse (Electronic Fuse)
【職位描述】
設計RVI公司新創的光通訊引擎(Optical Engine)類比電路設計工程師,負責設計、開發、測試、優化和調試類比電路及系統,產品矽中介層、玻璃中介層與高階基板。負責從概念到生產的電路設計,確保光引擎達到品質和性能標準。
【主要職責】
1.設計和開發創新的類比電路和系統,應用於光引擎和相關技術領域。
2.測試、優化和調試類比電路,確保其性能符合設計規範和功能需求。
3.與跨部門團隊合作,包括系統工程師、軟體工程師、光學工程師及其他專業人員,共同實現產品開發目標。
4.與客戶密切合作,理解其需求並提供技術支持和解決方案。
5.制定和執行測試計畫,分析測試數據,並提出改進建議。
6.保持對最新技術趨勢的了解,並將其應用於產品設計中以提升競爭力。
Position Description:
As an Analog Circuit Design Engineer at RVI, you will be a key contributor to the development of our next-generation Optical Engine. You will be responsible for designing, developing, testing, optimizing, and debugging analog circuits and systems used in advanced optical communication modules, including silicon interposers, glass interposers, and high-end substrates. This role spans from initial concept to mass production, ensuring the performance and quality of the optical engine meet industry standards.
Key Responsibilities:
1.Design and develop innovative analog circuits and systems for optical engines and related applications.
2.Test, optimize, and debug analog circuits to ensure performance meets design specifications and functional requirements.
3.Collaborate with cross-functional teams, including system engineers, software engineers, and optical engineers, to achieve product development goals.
4.Work closely with customers to understand their requirements and provide technical support and tailored solutions.
5.Develop and execute test plans, analyze test data, and propose design improvements.
6.Stay updated on emerging technologies and incorporate relevant advancements into circuit design to enhance product competitiveness.
Job Summary:
Layout Engineer will work directly and indirectly with Design / CAD / Layout Manager in development of Mixed-Signal and Analog Integrated Circuits. Individual perform job professionally and independently. The following are the requirements for this job function.
Essential Functions:
• Chip Planning
• Project Schedule / Layout Schedule Estimation
• Device Placement on block level according to matching requirements
• Block implementations on Top Level
• Top Level connections
• Signal matching / sensitive nets shielding technique
• Chip power / ground planning
• Integration of Analog top with Auto-Placement-Routing
• Pad / ESD rule and routing / connection
• Database DRC & LVS verifications on either DIVA or Dracula basis
• Chip Tape-out in accordance with company’s Tape-out Procedure
• Positive Attitude
Qualifications:
• 3+ years Layout experience in Analog and/or Mixed-Signal Circuit Design
• Ability to do chip plan, estimate die size and project schedule
• Ability to resolve DRC & LVS data verification and tape out chip independently
• Familiarity with fundamentals of analog processes
• Experience with Cadence and/or VIRTUOSO tools preferable
1. 16bit ADC/DAC design experience
2. PLL/DLL/RF/OSC/POR/LVDS design experience
3. LDO/DC-DC design experience
4.Guide layout engineer to make a compact & working layout