「(SoC Team) 資深數位IC設計工程師 (Dram Subsys) （*此職缺非研發替代役*）」的相似工作

1.數位IP相關功能的設計與實現 2.數位IP仿真與FPGA驗證 3.數位IP/subsys/chip_top的前段整合流程signoff 4.ISO 26262 FMEDA 設計和品質改進 5.與第三方數位 IP 供應商合作

[About Us] Quantrend Technology focuses on building financial trading strategies across a variety of asset classes and global markets. We empower the paradigm shift from traditional quant to AI quant by using modern end-to-end deep learning models. The difference between traditional approaches and our proprietary solution is that our models can automatically extract robust and high-quality trading signals (Alphas), but traditional hand-crafted approaches often fail to do so. We are a performance-driven company, seeking agile and talented people to join our team. Our working environment is relaxed yet intellectually intense. If you are a tech-savvy individual who enjoys the challenges of solving difficult technical problems in a fast-paced, energetic environment, then this is the role for you. We value the contributions of trading strategy developers and offer lucrative dividends and annual bonuses to high-performance employees. If you ever imagine running your startup where the profits are directly associated with your efforts, join us now! [Responsibilities] - End-to-end research and development, including alpha idea generation, data processing, strategy backtesting, optimization, and production implementation. - Perform rigorous and innovative research to discover systematic anomalies in the market. - Identify and evaluate new datasets for alpha generation. - Collaborate with machine learning alpha research and engineering teams to generate practical trading signals. - Conduct quantitative research independently including market data analysis, prototyping, backtesting, strategy parameters tuning, and performance monitoring. - Design and maintain trading models and strategies framework with the backend engineer team. Trading models and strategies execution implementation and market monitoring. - Maintain and improve portfolio trading in the production environment. [Requirements] - Degree in mathematics, physics, computer science, finance, business school, or with other quantitative-related experience. - Interest in quantitative research and statistical evidence-driven decision-making. - Experienced in trading crypto, equity, FX, options, or futures will be a plus. - Programming skill in Python is a must, experience with C++ or Rust is a plus - Strong analytical and quantitative skills are a must. - Ability to development of trading models or strategies independently. - Demonstrated ability to conduct independent research on alpha factors. - Ability to design and figure out innovative alternative alpha factors as trading signals.

1. 熟讀規格書，建立VPLAN 2. 使用SystemVerilog 程式語言設計，UVM 建立模擬環境 3. 執行CRT驗證流程 (使用使用VERDI VCS NC等工具) 4. 跨部門合作溝通 (設計&軟體等部門)

1. Project integration support & implementation, to deliver qualified nestlist from RTL. 2. preSTA/SYN/LEC/postSTA/etc. EDA flow execution and enhancement 3. Timing & power closure 4. Schedule control, netlist optimization, flow coordinator

※ Job Contents: 1. DDR/HBM controller IP design 2. DDR/HBM IP customer support 3. Execute digital IP front-end flow ※ Requirements: 1. 3-years digital IC design experiences 2. Senior/Technical Manager: 8-years digital IC design experiences 3. Familiar with DDR protocol is a plus 4. Familiar with AMBA interface is a plus 5. Familiar with IC front-end design flow such as Lint/CDC, Synthesis, LEC/formality, PrimeTime STA is a plus

Key responsibilities: • Perform IC design of FTDI products • Perform Verilog RTL design to meet product specifications and requirements • Perform front-end verification using UVM methodology • Work with Systems and Software engineers on FPGA verification • Perform Logic Synthesis, Static Timing Analysis • Lead DFT related activities - Scan Insertion, ATPG, Pattern Validation • Work with Physical designer to achieve timing closure • Work with test team in debugging production test issues • Help debug & correct any functional issues found in taped-out devices • Participate in design reviews, support ISO processes and documentation Additional responsibilities: a) Any reasonable task assigned by management and deemed to be within the individuals’ capabilities to ensure smooth running of the business. b) As this is an evolving business, ongoing change is an integral part of the position. Management will liaise with the individual on any fundamental change to work practices. The individual is required to embrace and adopt any change to working practices. Knowledge and skill requirements: • Degree/Master in Electrical/Electronic Engineering • 5 years or above experience in the area of digital IC design • Working experience from design to tape-out are essential • Experience in Verilog HDL and VHDL RTL design, OVM/UVM verification methodology , Logic Synthesis, DFT, ATPG, Timing Closure • Experience in using EDA tools from Cadence, Synopsys • Knowledge and working experience in one or more of the following: o Digital and mixed-signal design o USB interface products o Knowledge in connectivity technology such as USB, UART, SPI, I2C o Project Management Working conditions:  Working conditions are normal for an office environment.  Work requires willingness to work a flexible schedule.

1.客戶FPGA and SoC 技術相關問題處理 2.FPGA and SoC 設計技巧教育訓練 3.Xilinx 產品推廣

• Co-work with package design team to complete a substrate layout that will meet the design objectives for performance, cost and quality. • Co-work with SOC team to complete Bump floorplan and RDL routing. • Power mesh/power density flow development and related flow development and enhancement. • Provide power plan result for PR team. • Chip IR signoff : provide the result and solution to APR & package team • Chip level PEM/SEM simulation and fixing plan providing. • SIR/DIR/PEM/SEM result data review and verification. • Familiar with Voltus / Redhawk experience is required.

我們專注於3D影像立體雙目視覺技術 產品應用於3D 影像辨識、360 度環景拍照、攝影或AR 與VR 職務內容： ★ USB2.0/3.1或 MIPI 介面之2D/ 3D 影像處理與壓縮之 IC 開發 ★ 影像處理與壓縮相關數位 IP暨產品之開發設計、測試、驗證 條件要求： 1. 對IP Verification, System Verification 有興趣 2. 熟Verilog coding 與 ASIC design Flow 與 Timing Closure 3. 或有 SoC IC 開發經驗 4. 對開發人工智慧((AI) 晶片與邊緣運算有興趣者

1. 主動式電子掃描陣列 (相控陣列) 雷達系統之數位控制。 2. 熟悉Verilog與FPGA開發流程，了解High-Level Synthesis開發技術。 3. 具有實作數位訊號處理與數位架構設計於FPGA之經驗。

1. USB3.0 host/device開發驗證相關工作 2. RTL coding/synthesis/simulation/verification

Job Description: In this position the individual will develop test environment, test plan, and test cases based on the product specification and related industrial standards. The individual will require initiating a test plan review with the team and updating the test plan accordingly. The candidate will require executing and developing the test cases based on test plan, debugging and reporting the test result to achieve full function coverage goal. The individual will require developing ASIC bench functional test programs and doing ASIC bring-up and ASIC bench testing. The ideal individual must have proven ability to achieve results in a fast moving, dynamic environment. The candidate must have ability to coordinate priorities and initiatives and clear communication skill.

【在華邦，學習不設限，讓AI技術力與你的未來力同步成長!】 我們深信「人才永續」是企業創新的核心動能。華邦持續投資於數據素養與AI應用的培育，支持每一位人才掌握AI與數據應用的核心能力。 ．內部學習平台提供超過4,000堂線上課程，其中包含近850堂資料科學、人工智慧、數據思維與程式技術等多元主題，支援彈性自主學習 ．建立跨部門的 AI實作班與技術社群，定期舉辦研習與交流活動，讓知識轉化為實戰力 ．完善數據應用學習資源，結合資料呈現(Power BI、Tableau)、資料處理(Python、JMP)、流程自動化(Power Automate、UiPath)、AI助手(Copilot)，協助同仁有效以數據驅動決策與創新。 ．搭配專業語言學習平台，提供學習補助與資源，鼓勵同仁持續進修，拓展國際視野 無論你是技術新秀還是資深專才，華邦鼓勵所有領域都能與AI結合，與國際接軌。持續精進、突破自我！ 【邀請您將104履歷同步上傳至華邦官方網站，將使您的履歷優先被主管看見】此職缺履歷登錄網址:https://bit.ly/4mmbZ92 [工作內容] 1. Develop and maintain DRC related Calibre SVRF/TVF rule deck and tech file. 2. Develop and maintain dummy-fill utility to enlarge margin of processes. 3. Support designer/layout to fix design rule related issue. 4. Maintain Laker GUI for layout users. 5. Build and optimize automation flows (Python/TCL/Perl).

About Ubiquiti At Ubiquiti Inc., we create technology platforms for Businesses, Smart Homes, and Internet Service Providers, driven by our goal to connect everyone, everywhere. To date, Ubiquiti has shipped over 100 million devices worldwide, from ISP networking products to the next generation of IT solutions. Our growth is made possible by the dedicated team of hundreds behind the scenes. From software developers and product managers to designers and strategists, Team UI is driven to achieve our common goal: Rethinking IT. At Ubiquiti, you’ll heighten your potential and broaden your horizons, all while shaping the future of connectivity. Role Summary We are seeking a highly motivated hardware engineer to join our team developing enterprise-grade network and storage products, including WiFi routers, Switches, Storage, and Server systems. This role will be responsible for hardware architecture design, schematic development, system integration, validation, and cross-functional collaboration throughout the product lifecycle. The candidates will have a strong background in digital circuit design, system-level thinking, and experience with high-speed interfaces such as DDR, Ethernet, PCIe, and so on. You will collaborate closely with layout, mechanical, RF, DQA, firmware, and manufacturing teams to deliver robust and scalable hardware solutions. Also, one must be very aggressive in providing suggestions and comments at the design stages and thinking widely, and making decisions for designs. Responsibilities - Lead or contribute to hardware architecture planning, including CPU/SoC platform selection, Ethernet switch/PHY ICs, Interface solutions, and high-speed interfaces (PCIe, Ethernet SerDes, USB, SATA). - Design and review schematics, select components, and manage and optimize BOM for cost, quality, and manufacturability. - Collaborate with layout engineers to optimize PCB stack-up, impedance control, signa,l and power integrity. - Work with RF, DQA, and SI teams to validate functionality, debug issues, and ensure product performance and reliability. - Define and execute hardware validation test plans, document results, and assist in root cause analysis. - Experience with EMC/ESD design and debugging techniques. - Evaluate and recommend updates for DFC (Design for Cost), DFM (Design for Manufacturing), and DFA (Design for Assembly). - Tear down competitor products to assess system architecture and solution. - Provide regular updates on project status and coordinate with cross-functional teams to align milestones and deliverables. Requirements - MS degree in Electrical Engineering or a related field. - Solid understanding of system-level hardware architecture for Networking, Storage, Server products, and RF fundamentals. - Hands-on experience in digital circuit design, high-speed interface design (PCIe, Ethernet SerDes, USB, SATA), and power management (LDO, DC-DC, PMIC). - Familiar with schematic and PCB design tools such as OrCAD, Allegro, or PADS. - Proficient with lab equipment such as oscilloscopes, logic analyzers, network analyzers, and power supplies. - Strong communication and teamwork skills, capable of working in a fast-paced, cross-functional environment. Preferred Qualifications - Experience in enterprise Switch/AP Router, Storage, or Server system hardware development. - Highly organized in managing hardware platforms and proactive in developing innovative product concepts. - Strong self-motivation with a proven ability to drive complex technical issues to resolution. Benefits - An international work environment with opportunities to collaborate closely with global development teams. - Excellent working conditions in a supportive and innovative atmosphere. - Competitive compensation package, including attractive salary, perks, and benefits. - Comprehensive group and health insurance coverage. - Complimentary drinks and snacks are available in the office.

1.Support Design Engineer on Signal Integrity testing and Debugging on Chip and Demo Board 2.Support Customer projects design-in stage to mass-production. 3.Support Customer projects design review (Schematics, layout, CTS report) 4.Team work with RD, AE and QA on debugging and problems solve.

DRAM數位邏輯電路設計 『具工作經驗者，薪資另議』

Job Title: NPU Modeling Engineer Job Description: Overview: We are seeking an experienced NPU Architect to join our team. As an NPU Architect, you will play a crucial role in designing and implementing the hardware model for our Neural Processing Unit. Your expertise will be instrumental in ensuring efficient and accurate execution of neural network workloads on our NPU. Responsibilities: 1. NPU Architecture Design: • Collaborate with cross-functional teams to define the architecture and specifications for the NPU. • Design the NPU's core components, including the PE array, memory hierarchy, and control logic. • Optimize for performance, power efficiency, and scalability. 2. Bit-True Hardware Model Implementation: • Develop a bit-true hardware model of the NPU in C language. • Ensure that the model accurately represents the NPU's behavior, including arithmetic operations, memory access, and control flow. • Validate the model against reference neural network workloads. 3. Cycle-Accurate Modeling: • Create a cycle-accurate model of the NPU to simulate its behavior at the clock cycle level. • Account for pipeline stages, data dependencies, and timing constraints. • Use tools like Verilog, system-Verilog, or specialized simulation environments to achieve cycle-accurate modeling. 4. Performance Analysis and Optimization: • Profile the NPU model to identify bottlenecks and areas for improvement. • Propose and implement optimizations to enhance performance and reduce latency. • Collaborate with software teams to fine-tune the NPU's behavior. 5. Verification and Validation: • Create testbenches and test vectors to validate both the bit-true and cycle-accurate models. • Conduct functional and performance testing to ensure correctness and compliance with specifications. • Debug and resolve any discrepancies between the models and the actual NPU. 6. Documentation and Communication: • Document the NPU architecture, design decisions, and implementation details. • Present findings, progress, and challenges to stakeholders and management. • Collaborate with software engineers, firmware developers, and system architects. Qualifications: • Master's or Ph.D. degree in Electrical Engineering, Computer Science, or a related field. • Minimum of 3 years of experience in NPU architecture design and implementation. • Proficiency in C/C++/Verilog/System-Verilog programming for hardware modeling. • Familiarity with systolic arrays, matrix multiplication, and neural network accelerators. • Knowledge of bit-true modeling, fixed-point arithmetic, and floating-point arithmetic. • Experience with verification tools and simulation environments. • Strong analytical and problem-solving skills. • Excellent communication and teamwork abilities. • Attention to detail and commitment to quality. If you are passionate about NPU architecture, hardware modeling, and want to be part of a team driving innovation, we encourage you to apply. Join us in shaping the future of AI!

1. Participate in digital design specification, architecture definition, and microarchitecture planning. 2. Conduct FPGA prototyping, testing, and debugging of digital IP designs. 3. Collaborate closely with analog/mixed-signal design teams, firmware engineers, and system engineers to ensure successful product integration. 4. Develop, implement, and verify RTL code (Verilog/SystemVerilog) for high-speed Serdes interfaces including USB, DP, HDMI, DDR and PCIe.

This role will focus on developing quantitative algorithmic CTA and high-frequency trading strategies using machine-learning-driven and data-driven methodologies, you will need to think about how to exploit modern machine-learning techniques on diverse financial data sets. It's quite different from other typical machine learning jobs because our percentage-based lucrative dividends and annual bonuses are directly associated with your model's performance! You will also have the opportunity to conduct independent algorithmic research. The main programming languages are Python and Rust. 【About Us】 Quantrend Technology focuses on building financial trading strategies across a variety of asset classes and global markets. We empower the paradigm shift from traditional quant to AI quant by using modern end-to-end deep learning models. The difference between traditional approaches and our proprietary solution is that our models can automatically extract robust and high-quality trading signals (Alphas), but traditional hand-crafted approaches often fail to do so. 【Responsibilities】 1. Conduct quantitative research, and apply advanced modern machine learning methods to diverse data sets to build robust models for forecasting financial market risks and returns. 2. Design and implement algorithmic CTA and high-frequency trading strategies including backtesting and evaluation. 3. Research / propose/validate new effective financial market predictive features, models, and trading strategies. 4. Design and implement directional movement/volatility/risk/price impact/slippage forecasting models in CTA and high-frequency trading. 5. Deep reinforcement learning-based optimal control of trade execution, risk management, and portfolio construction. 6. Self-supervised / unsupervised learning on financial market data sets. 7. Co-work with trading system developers to deploy trading strategies in live trading environments. 【Requirements】 1. Advanced training in Mathematics, Statistics, Physics, Computer Science, Electrical Engineering, Financial Engineering, or another highly quantitative field. (Bachelor’s, Master’s, Ph.D. degree) 2. Strong knowledge of probability, statistics, machine learning, deep learning, time-series analysis, pattern recognition, computer vision, NLP, etc. 3. Strong programming skills in Python machine learning packages, including NumPy, pandas, scikit-learn, XGboost, Tensorflow, and Keras or PyTorch. 4. Solid experience in EDA (exploratory data analysis) using Python, familiarity with data visualization using packages including matplotlib, seaborn, etc. 5. Deep understanding of machine learning theories and algorithms, with the ability to debug ML models, tune hyperparameters, and identify and solve the root cause of model performance bottlenecks. 6. In-depth understanding of deep learning theories, network architecture design, and training/optimization techniques, with hands-on experience in the development of deep learning models. 7. Superb analytical and quantitative skills, understanding of and experience with mapping domain problems into algorithms, along with a healthy streak of creativity. 8. Entrepreneurial, highly-productive, extremely detail-oriented, with a sense of ownership of his/her work, working well both independently and within a small collaborative team. 9. Great communication and problem-solving skills. 10. Self-motivated and fast-paced learner. 【Nice to Have】 1. Bachelor’s degree in financial engineering. 2. Experience in trading and in-depth knowledge of financial markets. 3. Prior experience working in a data-driven research environment. 4. Experience in training DRL (Deep Reinforcement Learning). 5. Bayesian / hierarchical probabilistic graphical modeling experience. 6. Experience in algorithmic trading. 7. Knowledge of SQL and NoSQL databases and Docker containers. 8. Experience with AWS.

1.RTC Module/ IP design. 2.Design synthesis. 3.Design verification. 4.DFT/ siemens tools.