「(SoC Team) 資深數位IC設計工程師 (SoC Top Integration) （*此職缺非研發替代役*）」的相似工作

我們專注於能源晶片與深度演算法的融合創新，誠徵SoC系統架構工程師，加入我們打造次世代電力分析專用SoC晶片的行列，透過系統整合驅動硬體創新，徹底改寫電力分析解決方案的效能與整合度天花板。 你將負責： 設計SoC系統架構和功能分割，定義數位與類比功能區塊 開發SoC內部互連架構和資料流路徑最佳化方案 協調數位IC和類比IC的功能整合與系統驗證 建立SoC設計流程並進行系統效能與功耗優化 我們期待你具備： 碩士以上學歷，熟悉完整SoC設計流程（規格→架構→實現→驗證） 精通SoC系統架構設計（CPU/DSP、記憶體階層、匯流排架構、電源管理） 熟悉RTL設計、SystemVerilog/VHDL與SoC驗證方法學（UVM等） 具備SystemC、MATLAB/Simulink系統建模與EDA工具鏈操作能力 加分條件： 有電力電子、電源管理或混合信號SoC整合經驗 熟悉DSP或專用處理器架構設計 具備先進製程節點（28nm以下）設計考量經驗 有成功的SoC tapeout和量產經驗 如果你熱愛用系統整合重新定義電力分析晶片的可能性，歡迎加入我們，打造更智慧的硬體未來！

我們專注於3D影像立體雙目視覺技術 產品應用於3D 影像辨識、360 度環景拍照、攝影或AR 與VR 職務內容： ★ USB2.0/3.1或 MIPI 介面之2D/ 3D 影像處理與壓縮之 IC 開發 ★ 影像處理與壓縮相關數位 IP暨產品之開發設計、測試、驗證 條件要求： 1. 對IP Verification, System Verification 有興趣 2. 熟Verilog coding 與 ASIC design Flow 與 Timing Closure 3. 或有 SoC IC 開發經驗 4. 對開發人工智慧((AI) 晶片與邊緣運算有興趣者

※實際任用職稱依個人相關經歷敘薪。 1.各類平面顯示器驅動晶片數位電路設計 2.參與新產品開發規格定義、區塊規劃、設計模擬、整合和驗證 3.與類比、系統和佈局設計工程師溝通合作，共同研發最具競爭力的產品 4.開發CP 測試程式，從 CP 測試程式流程實際驗證所設計數位電路之可測試性

- Experience with memory controllers (e.g. DDR DRAM, eMMC and other flash, etc.) - Experience in CPU or various buses (AXI, etc) - Good verilog writing skills - Willingness to work with a variety of tasks

1. 主動式電子掃描陣列 (相控陣列) 雷達系統之數位控制。 2. 熟悉Verilog與FPGA開發流程，了解High-Level Synthesis開發技術。 3. 具有實作數位訊號處理與數位架構設計於FPGA之經驗。

1. Integrate DDR controller/phy related IPs. 2. Analysis design and verify DDR controller/phy. 3. Maintain and improve ASIC design/verification environment. 4. Maintain DRAM Mass Production ICs and issue Tracking/debugging.

在宏成半導體，我們重視的是 態度、能力與學習意願，而不是任何單一的學歷或出身背景。過去我們曾與不同背景、不同專長的人才合作，他們都能在這裡找到發揮專長的舞台。 我們相信： 多元背景的人才 都能在這裡發揮價值。 重要的是 專注學習、願意承擔、樂於挑戰，而不是來自哪個學校。我們的研發方向屬於前瞻領域，團隊規模雖然不大，但每一位夥伴的努力都能 直接影響專案成果。因此，我們非常珍惜每一次面試機會，也希望雙方能在溝通時誠懇交流，確認彼此是否適合長期合作。 如果對公司的文化或制度有任何疑問，歡迎您在面試時直接提出，我們會誠實回應，並期待找到 真正志同道合 的夥伴，一起實現願景。 AI 邊緣運算 IC / IP 設計 RTL Coding / Functional Verification FPGA 驗證與系統整合

This engineer will be responsible for designing and developing digital circuits of liquid crystal on silicon (LCoS) backplanes. You will encompass the entire digital design flow, including specification generation, architecture development, RTL description using System Verilog, verification via developed test benches, logic synthesis, executing place & route tools, and static timing analysis. Key Responsibilities •Lead the design of interfaces for liquid crystal phase modulator pixel arrays, such as column drivers, row drivers, and pixel bias drivers, as well as supporting clock and reset analog circuits. •Define specifications with the module architecture/system engineers. •Review, assess, provide feedback, and develop digital micro-architectures. •Generate RTL to comply with specifications, both manually and through automated generation. •Create a Cadence schematic database of digital blocks using Virtuoso. •Perform System Verilog verification simulations for the design by creating test benches at the block level. •Execute logic synthesis and generate the physical layout. •Create DFT hooks and generate test patterns. •Execute remaining back-end tools, including place & route, static timing analysis, and ATPG. Requirements •BS or MS with 2+ year experience. •Proficiency in System Verilog/Verilog language and simulation. •Proficiency in scripting languages such as Python, TCL, UNIX/LINUX shell, PERL, C/C++. •Experience with synthesis and static timing analysis. •Experience with place & route using Cadence Virtuoso, and verifying database vs schematics. •Knowledge of System Verilog assertions and functional coverage. •Experience with formal verification. •Familiarity with scan testing and participation in design reviews. •Excellent analytical, problem-solving, and debugging skills. •Good communication and teamwork skills, with the ability to work effectively in cross-functional teams. Preferred Qualifications •Knowledge of analog mixed-signal design. •Knowledge of SerDes circuits/IP. •Knowledge of LCOS or LCD IC architecture, column driver, MIPI interface. •Good understanding mixed-signal design and EDA tool configuration/setup. •Knowledge of liquid crystal phase modulators.

1.Work with team members and apply design techniques to work on different phases of complex logic design for ASIC/SOC project. 2. Working on the following tasks from time to time: HDL coding, documentation, RTL quality check, cooperate with back-end engineer etc.

1.RTC Module/ IP design. 2.Design synthesis. 3.Design verification. 4.DFT/ siemens tools.

1.影像應用或訊號處理 IC 研發 2.對數位影像、訊號處理, Verilog/VHDL, 具FPGA design flow 經驗。

1. 具 0~2年數位晶片設計，或有 0~5年類比晶片設計工作經驗。 2. 具備基本數位和類比電路知識，熟習標準晶片設計流程。 3. 熟習業界常用EDA tools, 或Matlab/ Simulink。 4. 研習過CMOS or BiCMOS 類比設計電路課程，對放大器有基礎認識。 5. Experience in these areas is preferred： * BiCMOS or CMOS high-speed (>20Gb/s) circuit, Linear electrical amplifier & equalizer, High-speed (>25G) CDR/PLL/SerDes. * Linear optical laser driver & receiver (TIA + linear amplifier) 本職位負責類比IC電路的設計、驗證和除錯。這是一個高度技術性的職位，對公司的產品開發至關重要。我們正在尋找一位熱愛類比IC設計並具有相關經驗的人才，以推動公司的技術創新和發展。 如果您對這個職位感興趣，請投遞您的履歷表，我們立即與您聯繫。

Job Description: In this position the individual will develop test environment, test plan, and test cases based on the product specification and related industrial standards. The individual will require initiating a test plan review with the team and updating the test plan accordingly. The candidate will require executing and developing the test cases based on test plan, debugging and reporting the test result to achieve full function coverage goal. The individual will require developing ASIC bench functional test programs and doing ASIC bring-up and ASIC bench testing. The ideal individual must have proven ability to achieve results in a fast moving, dynamic environment. The candidate must have ability to coordinate priorities and initiatives and clear communication skill.

【本職缺優先審核至高通官網投遞人選】請至高通官網上傳英文履歷表: https://qualcomm.wd12.myworkdayjobs.com/External/job/Hsinchu-City-TWN/SRAM-Characterization-and-Modeling-Engineer_3078557 【Talents who apply job through Qualcomm Career Website will be reviewed and considered as top priority】 https://qualcomm.wd12.myworkdayjobs.com/External/job/Hsinchu-City-TWN/SRAM-Characterization-and-Modeling-Engineer_3078557 【Job Description】 We are looking for talented and ambitious individuals to join the TECHIP team. The candidate should have a solid academic VLSI background and good software programming skills. Experience in industrial EDA tool automation and IP characterization is a plus. New graduates are welcome to apply. Minimum Requirements • Possess the basic knowledge of CMOS, FinFET logic and transistor, basic of digital circuit design optimization • Have Standard cell / Memory circuit knowledge & IP characterization background. • Strong logical and problem-solving skills with excellent analytical and debugging skills • Strong Software programming skills in Python or Perl in UNIX/Linux computing platform • Highly motivated, excellent team spirit and good communication skills. What makes you outstand : • Hands-on experience in industrial EDA tool automation, data analysis and visualization & large-scale software automation enablement. • Familiar with industry standard Design kit (DK) views, Liberty formats for foundation IPs (advanced modeling formats CCS, LVF) , statistical variation models & worked on development of the same. • Familiarity with front end pre-silicon design flow, RTL design/coding, logic design, Verilog/ System Verilog, RTL design verification, System Verilog Assertion (SVA), Design for Test, BIST modeling experience. • Experience in Static Timing Analysis, physical design is a plus. • Experience of spice simulation models, design rules verification procedures (like DRC/LVS/ERC) is a plus. Education Qualifications • Required: Bachelors, Electrical Engineering or Computer Engineering or Computer Science • Preferred: Master's, Electrical Engineering or Computer Engineering or Computer Science

SOC-NxSOC(next generation) team is hiring both junior and senior engineers, whose work scope is implement methodology development and PPA optimization from RTL to GDS. Join us, you will work together with expertise in all these areas; you will not only work for SOC development, but also enjoy and experience for all related products: smart phone/ tablet/ wearable/automotive etc.; you will work for the most advanced process/technology, the best chip in the world. What you'll be doing: - Methodology development at all stages, including synthesis, PnR, timing, IR, PV etc - PPA optimization What we need to see: - BSEE, MSEE is preferred - Project experience in IC design implementation - Courses taken in circuit design, digital design - Hand-on experience in EDA software from Synopsys (DC/FC-fe/FC-be/ICC2/PT/Formality), Cadence (Innovus), Ansys(Redhawk/RHSC) is preferred Ways to stand out from the crowd: - Proficient user of Perl, Python or TCL is preferred - Excellent English communication skill

Job Description We are seeking a highly skilled ASIC Verification Engineer to join our team in Chupei, Taiwan. In this role, you will be responsible for developing and implementing comprehensive verification strategies for complex ASIC designs, ensuring the highest quality and reliability of our semiconductor products. Develop and execute verification plans for complex ASIC designs Create and maintain testbenches using SystemVerilog and UVM Design and implement efficient verification environments Perform functional and formal verification of digital designs Develop automated test scripts to improve verification efficiency Analyze and debug design issues identified during verification Collaborate with design engineers to resolve functional discrepancies Generate detailed verification reports and documentation Stay updated with industry trends and emerging verification methodologies Contribute to the continuous improvement of verification processes and tools Qualifications Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field 5+ years of experience in ASIC verification with strong proficiency in SystemVerilog and UVM Experience with Verilog, VHDL, and industry-standard simulation tools (e.g., Synopsys VCS, Cadence Xcelium) Experience of CPU, GPU, NPU or HBM verification Knowledge of formal verification techniques and tools Strong debugging, problem-solving, and analytical skills Solid understanding of digital logic design, computer architecture, and communication protocols Excellent organizational skills with strong attention to detail Good communication and teamwork skills in a fast-paced environment

## 職務說明 - 應用於無人機雷達系統 - 數位IP架構設計與實作。 - 透過MATLAB/C++協助數位IP驗證 - 透過FPGA整合與驗證。 ## 技能要求 - 具備數位訊號處理經驗 - 具備數位電路設計經驗 - 程式語言必要：Verilog/VHDL, TCL, ##加分條件： - 具備雷達/通訊訊號處理、數位設計架構 - 具備RF/Analog 知識與RF/Analog校準設計 - 程式語言: MATLAB, python, c, c++, Chisel3

⚠️特別說明：此職位需on-site在新竹清大創新育成中心辦公室，無提供遠端工作條件。 ✅主要職責： 1. 高效能記憶體子系統（DDR/LPDDR Subsystem）之整合、開發與驗證。 2. 參與GenAI SoC設計，包括架構規劃、RTL設計、模擬與驗證。 3. 配合後端設計團隊，進行時序分析與設計優化。 5. 進行設計文件撰寫與維護，確保設計過程符合公司開發流程。 6. 針對客戶需求，進行系統分析與客製化設計開發。 ✅基本要求： 1. 電機、電子、資訊工程相關科系畢業，學士以上學歷。 2. 具備5年以上數位IC設計經驗。 3. 熟悉 DDR PHY 架構、控制器、timing calibration與 training 流程 4. 熟悉SoC Bus Fabric設計，具備AXI、AHB等匯流排介面經驗。 5. 熟悉RTL設計 (Verilog / System Verilog)。 6. 了解前端設計流程，包括模擬、合成、時序分析等。 7. 良好的問題分析能力，具備團隊合作精神。 ✅加分條件： 1. 有參與過 LPDDR Subsystem Integration與Silicon Tape-out 並成功量產 2. 熟悉 Synopsys LPDDR、Cadence GDDR IP/Subsystem 3. 熟悉 UPF、低功耗設計流程 4. 熟悉 DFT 、Scan、BIST ✅ Why Join Us 1. 與頂尖技術團隊共事，參與高效能 AI/高速記憶體解決方案開發 2. 自主創新文化，提供技術發揮與產品影響力兼具的工作環境

【工作內容】 1. 數位電路邏輯控制程式設計 2. 基本通訊界面控制 (UART/I2C/SPGIO/SPI) 3. CPLD規格評估 4. CPLD規格書規劃、撰寫、維護 5. Verilog/VHDL模擬除錯設計 6. CPLD測試、除錯、驗證及最佳化 7. 維護現有CPLD專案 【其他條件&加分項目】 1. 熟悉 Verilog, 2. 若具有 Altera Quartus II, Lattice Diamond , Modelsim能力佳 3. 具有開創性及解決問題的能力 4. 客戶導向及良好溝通技巧 5. 具備推動團隊完成任務的能力 6. 流程管理能力

Responsible for developing custom IP for SoC design from specification definition, circuit design to testing, and familiar with component and process characteristics.