「114年度研發替代役-VLSI Physical Design / APR工程師」的相似工作

1. Responsible for SOC physical implementation including floorplan, power plan, physical synthesis, clock tree, routing, RC, STA, timing closure, EM/IR, DRC/LVS to GDS out. 2. Responsible for APR physical design flow development & automation

(1)Must have BS in CS/EE of relevant experience in IC design field. (2)Familiar with IC design flow, placement and route (P&R), and layout. (3)Circuit knowledge and logic design relevant experience would be a plus.

1. Backend design tool and flow support - Innovus/ Calibre flow support 2. Timing / Power / SI convergence flow for backend flow 3. IR / EM flow tool usage support *備註：此職缺非研發替代役*

歡迎2026年畢業並正在找尋研發替代役的同學申請! 職位選擇: Direction 1: Physical Design Engineer Direction 2: ASIC Physical Design Engineer Direction 3: DFX Engineer Direction 4: CAD Tools Development Engineer Direction 5: Design Verification Engineer What you’ll be doing: Key Domains: • Physical and ASIC Design Implementation • Backend and Layout Optimization • Design-for-Excellence (DFX: Test, Manufacturability, Debug) • Development of CAD/EDA Automation Tools • Functional and Formal Design Verification What we need to see: • MS degree from EE/CS or related majors from a prestigious university. • Good knowledge in digital circuit design. • Experience in using Verilog HDL. • Experience in various EDA tools. • Fluent in English reading and writing. • Self-motivated, good team player. Ways to stand out from the crowd: • Proven ability to work independently as well as in a multi-disciplinary group environment • Good command of C/C++ or Verilog programming language. • Familiar with Perl/Python/Tcl/Shell scripting 應徵方式: 請提供以下資料： • 英文個人履歷 • 學士+碩士成績單 (中英文皆可) 提交申請: 請將上述資料投遞至104，符合資格者將會收到進一步的聯繫通知。

經歷不拘 1. Location：新竹 2. 大學以上電機、資訊相關科系畢業。 3 . APR實體設計工程師 4. Working on advanced node design methodology, PD execution and sign-off 5. Develop advance clock tree structure 6. Able to handle complex APR with 500+ hardmacros 7. Project analysis in early stage

歡迎2026年畢業並正在找尋研發替代役的同學申請! What You'll Be Doing: • Post-layout model extraction for project review sign-off • pre-layout model extraction for DOE • Work closely w/ Package and PCB Design teams to design and ensure link performance meets expectation before tapeout • Develop novel algorithms & new methodologies to improve SI/PI/EMI modeling efforts • Work w/ Application Engineering teams to support customers w/ SI/PI questions • Support signal integrity simulation and analysis for interfaces PCIE, NVLink, display, LPDDR etc. What We Need To See: • MS in EE and majoring in SI/PI technology or equivalent experience, • Strong understanding of electromagnetics, specifically electromagnetic waves including transmission line theory and via properties, and the SI/PI/EMI applications; S/Y/Z parameters; discrete signal processing knowledge • Know how to use ANSYS HFSS/Q3D/SIwave/Designer, Synopsis HSPICE, Cadence PowerSI, and Keysight ADS • Understanding of high-volume manufacturing variations and impact to channel signal integrity is a plus • Familiarity with high-speed I/O design concepts including clock generation, transmitter & receiver design, and equalization schemes • Familiarity with transient simulation in tools and understanding of eye diagram methodology • Exposure to lab measurements including VNA & TDR, and oscilloscope experience • Passionate about SI/PI work Ways To Stand Out From The Crowd: • SI analysis flow including frequency and time domain simulation • PDN analysis flow including model generation and time domain simulation • PSIJ Analyses involving co-simulation of circuits and PDN models • Experience w/ Matlab, Python, VBS, and C • RF/microwave engineering; EMI/RFI analysis capability 應徵方式: 請提供以下資料： • 英文個人履歷 • 學士+碩士成績單 (中英文皆可) 提交申請: 請將上述資料投遞至104，符合資格者將會收到進一步的聯繫通知。

*大學月薪33800元 / 碩士月薪38600元 1.申請與執行研究計畫。 2.負責報帳、經費申請、物品建檔等行政工作。 3.操作並維護計劃或實驗相關的設備與儀器。 4.協助資料收集和資料分析。 5.編輯、撰寫計畫報告書。

歡迎2026年畢業並正在找尋研發替代役的同學申請! We are seeking talented Firmware Engineers to join our team to work at the intersection of hardware and software, contributing to the core firmware that powers NVIDIA’s industry-leading GPUs and high-performance server products. In this role, you will design, develop, and optimize low-level software that enables reliable operation, high performance, and advanced features for both GPU and server platforms. These directions are: Direction 1: GPU Firmware Engineer Direction 2: Server Firmware Developer You’ll be doing: • Design, implement, and test embedded firmware for NVIDIA GPUs and server systems, enabling seamless hardware-software interaction. • Develop, maintain, and enhance bootloaders, device initialization code, and system management features. • Work closely with hardware, software, and systems teams to ensure robust bring-up and integration of new silicon and server platforms. • Diagnose, debug, and solve complex firmware and hardware-related issues across various development and production environments. • Drive innovation and optimization in areas such as power management, error handling, security, and performance monitoring for GPU and server hardware. • Contribute to documentation, compliance, and support for new product features and industry standards. Qualifications: • Master’s degree in Computer Engineering, Electrical Engineering, Computer Science, or related field. • Proficiency in C/C++ and embedded firmware development principles. • Understanding of computer architecture, hardware interfaces (I2C, SPI, PCIe), and real-time operating systems. • Experience with hardware bring-up, debugging tools, and low-level programming. • Strong analytical, troubleshooting, and communication skills. • Experience with server, GPU, or large-scale data center hardware is a plus. 應徵方式: 請提供以下資料： • 英文個人履歷 • 學士+碩士成績單 (中英文皆可) 提交申請: 請將上述資料投遞至104，符合資格者將會收到進一步的聯繫通知。

具備替代役男資格 對程式開發有高度熱忱

【研發替代役/預聘】數位IC設計工程師 工作內容： 1. SoC IC設計開發_TV演算法開發、模擬、驗證 2. IP數位電路的設計與驗證 3.驅動IC數位電路設計 【研發替代役/預聘】數位IC設計工程師 職務條件： 歡迎碩士以上電子、電機、電信、電控、資工等相關系所，具備以下經驗及專長： 1. 熟C/Matlab/Verilog HDL/FPGA/RTL Coding/TCL/Perl 2. 熟Synthesis flow/STA flow/DFT Flow 3. 熟Video/Audio codec/datapath 4. 熟RTOS與Embedded System 5. 熟任一高速界面如 USB, Ethernet, HDMI, DDR, DisplayPort 6. 熟影像處理、影像壓縮等相關設計 【共創A+聯詠】 穩健踏實、專家精神、創造優勢 驅動科技、開發創新、引領未來 邀請優秀人才，共創A+聯詠

▋ 關於德州儀器 德州儀器(TI)是位居類比晶片世界領導地位的半導體設計與製造公司，持續提供創新及頂尖的半導體技術與產品，協助客戶開發最先進的電子產品。除此之外，TI也針對在校學生及初入社會新鮮人設計完整的培訓制度與挑戰性的工作內容，並提供具競爭力的薪資與福利、完善的升遷管、輪調培訓計畫以及活潑與國際化的工作環境。 ▋科技菁英計劃 - TI 應用工程師輪調培訓計畫 有思考過RD、IC設計之外的另一種職涯可能嗎? 喜歡與人互動並充滿挑戰的工作卻又擔心新鮮人無法立即上手嗎? 別擔心! TI針對FAE新鮮人提供海內外全面且扎實的系列培訓課程， 透過課堂及工作日常的任務的學習，您將具備FAE應具備的各項知識與技能，在客戶面前成為專業與自信的FAE！ 另外，TI亦提供完整的輪調計劃，透過給予新人不同職務內容的學習， 使其能在公司有更多成長及發展的機會。 ▋ 應用工程師職務說明 >>在TI做FAE，您可以… • 參與FAE完整培訓計畫，包含1對1 coach、豐富教育訓練資源 • 與全世界技術專家合作，參與跨國會議及海內外輪調計畫，在國際舞台成長 • 接觸TI多元產品線，包含熟悉的#消費性電子、時下最夯的#車用電子 ，以及工業用等產品，共超過8萬顆產品，學無止境！ • 透過專案及團隊合作，快速累積技術硬實力及溝通軟實力 • 享受開放扁平的組織氛圍，不論是專業領域或職涯發展，都能夠勇敢表達 • 走出多元職涯，不論是技術導向的技術專家(technical ladder program) 或是領導團隊的用人主管，TI提供暢通的升遷管道讓您有機會被全世界看見 >>FAE在做什麼 作為“Technical Expert”，與Technical Sales Engineer併肩合作，了解客戶的技術需求、解決客戶的技術痛點，將TI產品特性與客戶系統需求聯結起來。運用產品選擇、系統、實現和調試方面的技術能力，從而實現業務目標。 • 積極與客戶建立關係，及時掌握客戶開案訊息，進而瞭解其需求與系統設計，推展TI的產品讓客戶的設計更有市場競爭力。 • 透過TI全球技術資源，提供專業技術服務，解決TI產品應用在客戶系統上的技術問題，協助客戶順利導入量產。 • 了解TI系統及產品，並研究同業競爭的狀況，反應客戶需求及市場資訊給研發團隊做為未來產品開發的參考。 看更多徵才資訊與FAE工作介紹=> https://www.facebook.com/texasinstrumentsTW/videos/1382188632429211 歡迎至https://www.cakeresume.com/resources/texas-instruments?locale=zh-TW 看更多內容 #R&D外的另一種選擇 #IC Design的另一種選擇 #結合技術及與人溝通 #探索不同產品之技術與應用 #走出多元彈性的職涯 #年薪(含紅利)百萬起跳 ▋ 面試準備: • Phone interview: 1. 對德州儀器及此職務的了解: o 針對德州儀器的業務範圍或是德州儀器在台灣的業務發展 2. 投遞動機 o 針對此職務為什麼想要投遞 o 對職務的了解程度 o 未來工作發展方向 • 第一關面試準備: 1. 英文自我介紹 2. 簡報(碩論題目或是DC/Amplifier介紹) • 第二關面試準備: 1. 針對工作內容了解 2. 職涯發展方向 3. 情境考題

1.IC Implementation & Verification - including floorplan, CTS, STA, IR-drop analysis, DRC&LVS. 2.Familiar with EDA tools including ICC , Encounter 3.TCL/perl script programming. 4.Low power flow is preferred.

操作EDA軟體完成晶片實現, 包含 : •電路元件規劃擺放,佈局與繞線 (Floorplan, Place and Route) •時序收斂 (Timing closure) •壓降分析與收斂 (IR-drop analysis and fixing) •實體規則驗證 (DRC/LVS/ERC) •設計變更 (ECO) •EDA Tools: DesignCompiler/Genus, DFTCompiler, ICC2, Innouvs, Formality/LEC, PrimeTime, Calibre, Voltus, Redhaw *參與先進製程晶片開發。 *完善教育訓練, 有機會一個月內學會APR工作流程。

We are looking for talented engineers to join our VLSI Verification team. You’ll work on next-generation SoCs, applying advanced verification methodologies (SystemVerilog/UVM, coverage-driven, assertion-based) and leveraging AI-assisted tools to accelerate testplan writing, assertion development, and debug. Responsibilities • Develop and execute verification plans for complex SoCs/IPs • Build testbenches, assertions, and coverage models • Collaborate with architects, designers, and post-silicon teams • Ensure correctness and reliability of cutting-edge designs Why Join Us • Cutting-edge verification with AI-powered flows • Work alongside global world-class engineers • Accelerated growth in a learning-driven culture If you are smart, curious, and eager to learn, join us and shape the future of silicon innovation! 我們正在尋找聰明好學的工程師，加入我們的 VLSI Verification 團隊。 這裡沒有高壓的文化，而是重視 自主、學習與創新。我們相信工程師應該能專注在真正有價值的問題上，並透過 simulation 與 formal verification 技術搭配 AI 輔助，大幅提升驗證效率。 工作內容 • 開發與執行 SoC/IP 驗證計畫 • 使用 simulation (模擬) 與 formal (形式驗證) 技術，確保設計正確性與可靠性 • 建立 testbench、assertion、coverage model • 與架構師、設計師及 post-silicon 團隊合作完成驗證流程 • 善用 AI 工具 加速 testplan 撰寫、assertion 開發與 debug 我們能提供 • 外商文化：自主彈性、無高壓管理，重視結果與學習 • 技術前沿：結合 simulation + formal verification 與 AI 驅動流程 • 成長環境：與世界級跨國工程師共事，快速提升專業實力 • 全球影響力：你的成果將應用於數百萬使用者的產品 如果你聰明、積極、樂於學習，想在自由又專業的環境中挑戰自我， 歡迎加入我們，和我們一起打造下一代晶片驗證技術！

【研發替代役/預聘】數位IC設計工程師 工作內容： 1. SoC IC設計開發_TV演算法開發、模擬、驗證 2. 驅動IC設計/觸控IC數位電路設計 3. IP數位電路的設計與驗證 4. WLAN MAC數位IC電路設計、驗證、軟硬體模擬、系統架構規劃 【研發替代役/預聘】數位IC設計工程師 職務條件： 歡迎碩士以上電子、電機、電信、電控、資工等相關系所，具備以下經驗及專長： 1. 熟C/Matlab/Verilog HDL/FPGA/RTL Coding/TCL/Perl 2. 熟Synthesis flow/STA flow/DFT Flow 3. 熟Video/Audio codec/datapath 4. 熟RTOS與Embedded System 5. 熟任一高速界面如 USB, Ethernet, HDMI, DDR, DisplayPort 6. 熟影像處理、影像壓縮等相關設計 【共創A+聯詠】 穩健踏實、專家精神、創造優勢 驅動科技、開發創新、引領未來 邀請優秀人才，共創A+聯詠

1.馬達控制韌體開發 2.自動化測試/參數調整軟體開發 3.技術服務自動化流程開發

1. Proficient in fundamental circuit structures (e.g., standard cells, IO), with the ability to simulate basic circuits using Hspice or Spectre. 2. Experienced in IO/IP planning, including bump/PAD placement and RDL routing. 3. Familiar with the integrated circuit (IC) design flow, capable of performing design, optimization, and verification using tools such as ICC2 or INNOVUS. 4. Knowledgeable in power analysis and IREM methodologies, with hands-on experience using Ptpx, Redhawk, or Voltus for power and IREM evaluation. 5. Experience in developing automation scripts using Python, Perl, TCL, or Shell is a strong plus. 6. Experience in layout design using Virtuoso or Laker is a plus. 7. Knowledge of one or more of the following domains is preferred: semiconductor processes, ESD protection, digital and analog circuit design, signal integrity, power integrity, timing analysis, physical verification, thermal analysis, and mechanical analysis.

1. 編碼器新產品新市場需求蒐集及規格訂定 2. 透過磁路模擬分析與研究，解決磁性編碼器問題與優化產品設計 3. 編碼器系統性能測試分析與研究 4. 編碼器位置計算演算法研究與優化 5. 編碼器精度提升演算法研究與優化 6. 編碼器問題異常排除與分析，包含規格設計、規格制定、製程問題、系統性整合問題 7. 主動接觸供應商並管理製程與QC規範，藉由國內外出差達成目的 8. 需至中國出差

歡迎2026年畢業並正在找尋研發替代役的同學申請! Direction 1: Product Test Engineer Direction 2: Structural Test Engineer Direction 3: System Level Product Engineer Direction 4: Product Development Engineer Direction 5: Silicon Validation Engineer Job Description: Join our dynamic engineering team and play a crucial role in ensuring the performance, functionality, and quality of world-class semiconductor products. We are hiring talented engineers for multiple interrelated domains—including product test, structural test, system-level evaluation, product development, and silicon validation. In this comprehensive role, you will be at the forefront of product innovation, enabling robust and reliable solutions from initial silicon to high-volume production. Key Responsibilities: • Product Test & Structural Test: Design, implement, and optimize test strategies for semiconductor products at both the chip and board level. Develop production test flows to screen for defects, improve yield, and guarantee long-term reliability. Collaborate with design teams to define test coverage and drive design-for-test (DFT) improvements. • System Level Product Engineering: Evaluate products’ functionality and performance within real system environments. Develop, execute, and analyze system-level test plans to assure device quality, stability, and customer satisfaction. • Product Development: Work cross-functionally from concept through product release to define product specifications, validate new silicon, and coordinate the transition from R&D to manufacturing. Address and resolve design, process, and testing challenges to ensure timely and successful new product introductions. • Silicon Validation: Plan and carry out post-silicon validation activities. Characterize silicon, debug issues found in hardware, and provide feedback to design and process teams for continuous improvement. Qualifications: • Master’s degree in Electrical Engineering, Computer Engineering, or a related discipline. • Solid knowledge of semiconductor device fundamentals and test methodologies. • Experience with IC testing equipment, system validation, or hardware bring-up is a plus. • Familiarity with scripting and programming (Python, C/C++, or similar) is desirable. • Excellent analytical, troubleshooting, and communication skills. • Ability to work collaboratively in a fast-paced, cross-functional environment. • English communication ability 應徵方式: 請提供以下資料： • 英文個人履歷 • 學士+碩士成績單 (中英文皆可) 提交申請: 請將上述資料投遞至104，符合資格者將會收到進一步的聯繫通知。

【本職缺優先審核至高通官網投遞人選】請至高通官網上傳英文履歷表：https://qualcomm.wd12.myworkdayjobs.com/External/job/Hsinchu-City-TWN/GPU-Compiler-Development-Engineer--up-to-Sr-Staff--Hsinchu-_3057774 【Talents who apply job through Qualcomm Career Website will be reviewed and considered as top priority】 https://qualcomm.wd12.myworkdayjobs.com/External/job/Hsinchu-City-TWN/GPU-Compiler-Development-Engineer--up-to-Sr-Staff--Hsinchu-_3057774 【Job Description】 The largest provider of premium mobile SoC (system on chip) solutions. Adreno GPU has been driving the mobile industry toward rich graphics and gaming experience on smartphones. Now its power efficient GPU technology becomes fundamental to enable some new exciting markets beyond the smartphone like VR/AR, IoT, AI, drone, autonomous driving. GPU compiler is a key component of overall graphics technology, especially in terms of its influence on application’s performance on GPU. We are looking for talented engineers to create world class GPU compiler products to enable high performance graphics and compute with low power consumption. 【Responsibilities】 This position will be responsible for research, development and delivery of Qualcomm's Adreno GPU compiler products to our worldwide customers. At same time, there will be opportunities to influence GPU hardware design based on experience on how our GPU compiler has been used by real world users. 【Minimum Qualifications】 * Good C/C++ programming skills * Good communication skills and teamwork spirit, reliable and self-motivated 【Preferred Qualifications】 * Compiler development. For example, LLVM or GCC * Graphics knowledge or graphics/game software development * DirectX, OpenGL/Vulkan, OpenCL, or CUDA compiler development * D3D/OpenGL/Vulkan/OpenCL/CUDA driver development