1.Support enterprise IT workplace services, including OA application.
2.Compose IT documents, such as SOPs, Manual and others
3.Support IT projects and routine operations
【Key Responsibilities】
• Conduct hardware (HW), firmware (FW), and software (SW) testing on pen and touch-related products.
• Plan and discuss test cases and test plans with internal or customers.
• Manage test schedules to ensure timely execution of test cases.
• Collaborate with PMs, FAEs, and R&D engineers to complete verification tests.
• Analyze and document test issues, then address them in the system.
• Perform Pen & Touch performance tuning, optimizing linearity, accuracy, and usability.
• Operate, maintain, and manage test equipment and performance testing instruments to ensure optimal functionality and support testing needs.
• Create and maintain Standard Operating Procedures (SOPs) to ensure consistency and efficiency in testing or tuning processes
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【職務説明】
• 針對手寫筆與觸控相關產品進行硬體(HW)、韌體(FW)及軟體(SW)測試
• 與內部團隊或客戶規劃並討論測試案例與測試計畫
• 管理測試時程,確保測試案例能準時進行
• 與專案經理(PM)、應用工程師(FAE)及研發工程師合作完成驗證測試
• 分析並記錄測試問題,並記錄在系統中
• 進行手寫筆與觸控效能調校,優化線性度、準確性與使用體驗
• 操作、維護並管理測試設備與效能測試儀器,確保其功能正常並支援測試需求
• 建立並維護標準作業程序(SOP),以確保測試或調校流程的一致性與效率
【工作內容】
• Work with team members and apply current functional verification techniques to perform and improve pre-silicon verification quality and product Time to Market
• Provide the technical leadership to the DV team for the project
• Work independently on various DV tasks and provide technical guidance to the DV team.
• Be involved technically in the porting/creation of the DV environment for the new design, block and chip level test plan creation and implementation, coverage analysis, and regression cleanup
【職務條件】
• Master’s degree in Electrical Engineering, Computer Science, or related.
• Good understanding of ASIC design verification flow.
• RTL coding with Verilog/System Verilog and familiar with front-end design flow and C/C++ programming experiences.
• Knowledge of Perl, OVL, SVA, SV, UVM, OVM, script programming, etc.
【其他條件】
• MSEE with a minimum of 5 years, or BSEE with a minimum of 8 years of experience in digital ASIC/SOC design verification
• MS/BS degree in EE or CS with expertise in digital IP/SOC design verification.