1."Chip+PKG+Board" modeling & co-simulation for pre-silicon SI/PI/EMC analysis.
2.Co-work with RD/CAD/SE for chip design-in SI/PI/EMC issue support.
3.Gbps interface SI/PI co-design and validation, such as DDR1~4, LPDDR1~4, HDMI, VBO, eDP, MIPI, etc.
4.Provide pkg/board-level SI/PI/EMC design guideline or reference design.
5. Familiar with transmission line theory.
工作地點:台北
This vacancy is open for talent pool collection. We will contact you if we have proper vacancies that fit with your profile.
Job Mission
Represent manufacturing and act as gatekeeper from manufacturing to D&E function
Add value in overall manufacturing processes such as forming, machining, joining, and assembling
Job Description
Contribute to the solution of faults and takes the necessary initiatives and practical decisions to ensure zero repeat
Identify gaps and drive assigned process improvement projects and successful delivery
Initiate and drive new procedure changes and projects
Develop and maintain networks across several functional stakeholders
Prioritize works and projects based on business situation
Transfer knowledge and train colleagues on existing and newly introduced products
Education
Master degree in technical domain (e.g. electrical engineering, mechanical engineering, mechatronics)
Experience
3-5 years working experience in design engineering
Personal skills
Show responsibility for the result of work
Show proactive attitude and willing to take initiative
Drive for continuous improvement
Able to think outside of standard processes
Able to work independently
Able to co-work with different functional stakeholders
Able to demonstrate leadership skills
Able to work in a multi-disciplinary team within a high tech(proto) environment
Able to think and act within general policies across department levels
Diversity and inclusion
ASML is an Equal Opportunity Employer that values and respects the importance of a diverse and inclusive workforce. It is the policy of the company to recruit, hire, train and promote persons in all job titles without regard to race, color, religion, sex, age, national origin, veteran status, disability, sexual orientation, or gender identity. We recognize that diversity and inclusion is a driving force in the success of our company.
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Purpose of this Position
深入研究高速訊號,在高速硬體電路Signal Integrity上提供最佳設計且確保生產品質
Major Areas of Responsibility
專案研發
- Perform high speed signal integrity simulation including 10G/40G、25G/100G、PCIE、SATA、DP、USB、DDR3/DDR4/DDR5.
- Perform pre-layout, layout constraint, and post-layout simulation processes.
- PCB stackup design and layout review for high speed signal and PDN.
- Build component models to ensure the correlation between SI/PI simulation and measurement.
- Solid SI experience in resolving technical issues and performing detailed analysis.
團隊合作
- Collaborating with EE teams to refine high-speed signal performance.
- Collaborate with the layout engineer to provide clear layout guidelines and enhance footprint optimization.
- Responsible for EMC system testing.
- Assist pre-sales activity of EMC test and measurement instrument.
- Online/On-site customer support from pre-sale to post-sale, including presentation, demonstration, training and application cases.
- Through providing technical expertise in broad range of complexity, contribute to build a long-term, trustworthy relationships with customers.
1. 針對高速介面進行信號完整性模擬。
SI simulation : TDR, S parameter,Eye diagram,Crosstalk..
2. 電路板電源完整性模擬。
PI simulation : IR Drop , PDN..
3. 對於佈局圖給予改良建議。
Polar應用及評估PCB & VNA材料選擇方式
4. 信號完整性異常除錯。