「[Malaysia Penang]AE - proFPGA Application Engineer」的相似工作

The Staff/Sr. Engineer, CPLD will be based in Taiwan Taipei Wugu Site. The Staff/Sr. Engineer, CPLD performs the responsibility for CPLD programming and validation in Server/Storage Projects request. What a typical day looks like: 1. Skilled FPGA/CPLD Design Engineer with strong capabilities in Server/Storage system and hardware-level design. 2. Responsible for development and integration of CPLD/FPGA that implement functionality on prototypes: spanning from low-level hardware sequence control, logic control & status for embedded systems, to high-speed links, to high level IP blocks, to custom hardware-accelerated algorithms & filters. 3. Work closely with Hardware, BIOS, BMC and Firmware team for CPLD/FPGA development. 4. Designing validation plan and development spec. 5. Debugging platform and systems issues. The experience we are looking to add to our team: 1. 3-10 years of working experience in Firmware development. 2. Familiar in Verilog RTL language. Experienced with CPLD/FPGA development on Lattice, Altera and Xilinx devices. 3. Experience with I2C, SPI, LPC, UART, PCIe protocol design 4. Experience with verification methodologies, RTL and gate level simulations and debug. 5.Good problem-solving skills. The information we collect: We may collect personal information that you choose to submit to us through the Website or otherwise provide to us. This may include your contact details; information provided in online questionnaires, feedback forms, or applications for employment; and information you provide such as CV/Resume. We will use your information for legitimate business purposes such as responding to comments or queries or answering questions; progressing applications for employment; allowing you to choose to share web content with others or; where you represent one of our customers or suppliers, administering the business relationship with that customer or supplier.

1. IC產品之研發與應用設計 2. 建立IC產品基礎規格並設計IC電路 3. 降低產品成本，提高IC品質，支援軟/硬體開發 4. 熟數位IC設計及相關工具 Verilog HDL、Cadence IES simulator 、FPGA tools、Synopsys DC

1. 硬體設計開發產品及對應車廠需求 2. 進行實車安裝/測試、樣品製作、零件承認流程 3. 製作開發件之量產圖出圖和相關資料 4. 分析產件之不良點及提出改善對策 5. 展示車輛電子部品安裝及拆卸 6. 專案相關技術之支援 7 .主管交辦事項

1. 硬體設計開發產品及對應車廠需求 2. 進行實車安裝/測試、樣品製作、零件承認流程 3. 製作開發件之量產圖出圖和相關資料 4. 分析產件之不良點及提出改善對策 5. 展示車輛電子部品安裝及拆卸 6. 專案相關技術之支援 7 .主管交辦事項 必備專長: 1. 電子電路量測設備(三用電表、示波器)使用 2. 電路板焊接、零件更換能力

Position Description: 1. To provide key technical support in digital IC design implementation, product demonstration, and sales presentations. 2. To demonstrate strong ability and to be hands-on in RTL-to-GDSII design methodology, including both challenging low power and high-performance designs. 3. Have real design experience including floorplan and partition, place, CTS, route, STA timing closure, Physical verification, RC extraction, Power Network analysis. 4. Assist in technical evaluation, assessment and delivery of concurrent ASIC/SoC designs. 5. To play a leading role among other team members, while receive little instruction on routine and general assignments. Position Requirements: 1. A bachelor's degree is essential and 3+ years’ experience in IC design, electronic engineering or computer science applications. 2. Ability to understand and articulate technical issues, (and knowledge of) design products and their applications. 3. Requires working knowledge of one or more programming languages, and effective communication and soft skills. 4. An MS degree and/or working experience in multi-nation IC design house/or familiar with EDI/Innovus product is a plus. 5. Good communication in English and good work attitude. 6. Be familiar with shell/Perl/Tcl etc. script language.

As senior/staff digital design engineer, this person is required to support all digital design activities on company products, design services as well as internal IP development. Below are the responsibilities: - Responsible for RTL Design and writing of test bench - experience in IP core design such as peripheral interfaces, CPU cores, digital controllers - Architecture review, RTL design, functional verification, post synthesis simulations. - Responsible for SOC system Integration & verification - Experience in SoC Architecture and Microarchitecture A - Experience in ARM CPU integration to SoC - Experience in SDRAM Memory Controller integration - Experience in interconnect matrix, AHB Bus Arbitration, multi-layer AHB Bus architecture - Experience in SoC Peripherals design: GPIO, RTC, UART, I2C, I2S, and SPI - Excellent in Verilog RTL coding and simulation - Familiar with FPGA prototype and verification - SD/SDIO relative experience is an added advantage. - AMBA Interface relative experience is an added advantage. - Knowledge in controller design (USB, PCIe, SATA, and Ethernet) is an added advantage. - Preferably done some FPGA prototyping in previous employment Desired Skills & Competency Requirement: - Verilog RTL coding - SoC design flow and SoC peripheral IP design - FPGA prototyping and emulation - System validation and verification - Characterization and the handling of test equipment - Digital front-end design, simulation and synthesis - Verification in system Verilog OVM - Low power synthesis methodology - Digital support on DFT and ATPG - Scripting in Perl, Python, TCL, UNIX, Linux

1. Lidar & 精密光機電產品 FPGA開發工程師 - 負責開發與設計光達及其他精密光機電產品FPGA數位邏輯電路 - 使用Verilog開發LiDAR相關功能與驗證 - 根據需求開發IP及功能驗證 - 熟悉Lidar、ToF、Radar相關開發經驗佳 2. 嵌入式系統開發工程師 - 負責光達及其他精密光機電產品嵌入式系統相關程式開發與驗證 - 具備嵌入式系統開發經驗(Linux、RTOS、Bare Metal開發經驗) - 周邊傳輸介面驅動開發經驗(MIPI、VDMA、URAT、SPI、I2C、Ethernet等) - 嵌入式系統平台整合和測試維護 - 熟悉LiDAR、ToF、Radar相關開發經驗佳

太陽能發電站的現場運行與維護，包括發電監控、定期檢查、設 備保養、太陽能板清潔及場地內除草硬體修繕等工作 比特幣挖礦機房設備日常管理和維護，包括礦機、網路設備和冷卻系 統等 處理常見礦機故障，提升設備運行效率 協助現場資產管理，確保設備安全及庫存控制 電力及網路設備故障判斷及常見問題排除 日常運行報表及年月報表 ■應聘要求 ● 電氣工程或相關電力、電腦資訊、電子機械專業的大學畢業生 ● 熟練操作日常電腦設備和基本 IT 系統 ● 具備電路及電氣系統的基礎知識 ● 能夠使用日語或者英文進行溝通 日常會話水平 ● 具備台灣汽車駕照 ■薪資與福利 工作地點 東京都／千葉縣 月薪：22萬-27萬日圓（根據工作經驗） 出差補貼：每天 10,000 日圓（美國、澳洲、印尼等） 工作時間：上午 9:00 – 下午 6:00 休息日：周休二日及日本國家法定節假日 公司提供日本住宿、機票、就職簽證！ 帶薪有休、獎金、雇用保險、社會保險、厚生年金、勞災保險

★馬來西亞廠正式啟動營運！駐外儲備幹部 強力招募中！ 誠摯邀請馬來西亞僑生加入我們的國際團隊！ 於台灣接受完整培訓，未來返回母國協助在地事業發展！ ✪提供多元職務類別： ▪ 生產作業管理 ▪ 品質管制 ▪ 採購與供應鏈管理 ▪ 工程技術支援 ▪ 生物技術管理 ▪ 倉儲與物流規劃 ▪ 會計及財務 ▪ 關務及進出口…等 ✩詳細職務內容請參考本公司各相關職缺內容。

1. 主FPGA與CPLD專案開發與維護 2. 熟RTL coding, 具Xilinx ISE/Vivado或Altera Quartus II專案設計經驗 3. 能與軟,韌,硬體等相關部門co-work 4. 具Xilinx PCIe 與 MIG DDR3/4系統整合經驗者佳

1.售前技術規格討論 - 產品介紹與規格說明 - 瞭解客戶需求與應用 - 規劃客戶網路架構與設定 - POC測試 2.售後技術支援 - Bare metal switch 軟體開發技術支援 - 軟硬體技術支援 - 技術訓練 - On site Support

1.負責進料採購、物料管控與調度，並與廠內生產及幕僚單位保持良好溝通。 2.與供應商協調材料交期，確保物料品質與到貨時間能配合生產進度。 3.執行採購相關專案，並直接對應品牌客戶及處理主管交辦事項。

1. 製程巡檢 在生產過程中定期抽檢產品 確保製程穩定並符合品質要求 2. 成品檢驗 檢查最終產品的外觀、尺寸與功能 判定是否可出貨或需返修 3. 品質異常處理 分析品質問題發生原因 協助制定並執行改善對策 4. 品質資料記錄與報告 填寫檢驗記錄與品質報告 彙整統計數據作為後續改善依據 5. 品質標準制定與維護 協助建立檢驗標準與作業指導書 定期更新文件以符合實際作業需求 6. 內部稽核與教育訓練 配合品質稽核作業與內部審查 對相關人員進行品質教育與操作訓練

歡迎日本當地留學生、就職中社員投遞 薪資、制度、福利: 依照日本當地法規條件為基準，薪資條件面議 About the job (駐廠工程師) o Location: Chitose, Hokkaido Japan. o Language: English　& JLPT N1 o Duration: Permanent o Interview Process: 3 rounds - final will be with the Country Manager What you will be doing o We contribute the support and provide unique customer value around in Japan Service Team. o We take everyone is important partner and respect each other’s’ opinion. o You can learn the advance technical skills and collaborate with leading customers across the globe. o Teamwork is ours’ spirit; we are the team to make impossible to possible. o Come as you are, do what you love and grow with team. What will you do as “Field Service Engineer”? o Provide project handling and customer support, including modifying, troubleshooting, diagnosing, installing, customer training, and repairing NOVA systems. o Act as the primary liaison between NOVA Japan and customers, overseeing system performance, data collection, reporting, and customer satisfaction. o Quantify system performance using statistical techniques, ensuring system-to-system matching. o Coordinate all service activities with customers to maximize system uptime. What will make you succeed in the role? o Continuous Learning: Never stop growing. o Open-Minded Collaboration: Communicate well, work effectively in teams. o Resilience under Pressure: Thrive in high-pressure situations. o Customer-Centric Focus: Prioritize excellent customer service. o Autonomy and Interpersonal Skills: Work independently yet excel in interactions.

Do you want to help create the future of healthcare? Our name, Siemens Healthineers, was selected to honor our people who dedicate their energy and passion to this cause. It reflects their pioneering spirit combined with our long history of engineering in the ever-evolving healthcare industry. We offer you a flexible and dynamic environment with opportunities to go beyond your comfort zone in order to grow personally and professionally. Sound interesting? Then come and join our team as Product Specialist/Senior Product Specialist. This position is not only a sales/application role in product promotion but also involve portfolio management role. Your mission and responsibilities: The successful candidate will be responsible for promoting and selling the CT & MI products, prepare proposal to customer needs and update product portfolio to current users. Primary responsibilities include: * Promote our full range of CT & MI products to the customers * Closely work with our application specialist through organizing and performing the demonstration and presentation to the customers * Gather market intelligence and formulate promotion strategies to drive the business * Able to manage tender submission and the whole process * Maintain good rapport with our customers. Your qualifications and experiences: Individuals who meet the following requirements or possess the equivalent combination of competence and experience are invited to apply: * University degree in Science, Engineering or related discipline * 2 - 3 years selling experience in CT & MI related products is preferred * Aggressive, independent with self-initiative * Strong communication, negotiation, presentation and documentation skills * Proficiency in both English and Chinese

1.負責各品牌總業務窗口，串連與管控開發樣品到接單，並順利完成量產出貨的相關進度。 2.督導廠內BOM組資料符合SAP規範並完成接單前上傳。 3.定期追蹤客⼾付款狀況，與客⼾維持良好關係，配合品牌各要求與政策並宣導廠內相關單位。 4.培養員⼯專業知識、品質觀念及團隊合作的精神，並有效與跨單位溝通協調。

1. SOC/IP 整合工作，從RTL到 Netlist 2. clock tree structure design 3. Lint / CDC check / Synthesis/ DFT/ LEC

ASIC design engineer responsible for post-RTL design flow. He/She will be responsible for block and /or chip level synthesis, timing closure, DFT generation, and ECOs. The responsibilities include but are not limited to. •    Improve the design methodology and flow. •    Synthesis, timing closure, and DFT support for various types of SerDes IPs ranging from 10Gbps to 224Gbps data rates for different applications. •    Collaborate with Analog/Digital design teams to deliver competitive SerDes IP solutions for all the Marvell product lines. •    Provide support to the product teams, for both pre and post-silicon

【About the role】 Hytech is seeking a forward-thinking Manager of Software Security Architecture to lead the strategy, development, and execution of a world-class application security program. This highly technical leadership role will define the vision for embedding security throughout the software development lifecycle (SDLC), including modern AI and machine learning platforms. The ideal candidate will have deep expertise in secure software development, application security engineering, CI/CD automation, and integrating security into traditional, cloud-native, and AI-enabled environments. You will lead a global team of security engineers, build scalable developer-focused security solutions, and shape security strategies across engineering, infrastructure, DevOps, and data science teams. What this job involves: [Program Ownership & Strategy]: 1. Own and advance the enterprise application security program, including vision, technical strategy, and execution. 2. Define and implement scalable, modern AppSec practices for cloud-native and AI-enabled development. 3. Represent application security in enterprise architecture, risk, and compliance initiatives. 4. Define KPIs to measure security posture and program effectiveness. [Leadership & Collaboration]: 1. Lead, mentor, and grow a global team of application security engineers and specialists. 2. Promote a proactive “shift-left” culture by embedding security throughout the SDLC. 3. Partner with development, DevOps, AI/ML, and product teams to integrate secure practices into software and data science workflows. 4. Build strong cross-functional relationships to drive security-first thinking and align investments with business value. [Security Tooling & Technical Implementation]: 1. Drive adoption and optimization of security tools (SAST, DAST, SCA, IAST, secrets scanning, etc.) in CI/CD workflows. 2. Design and deploy developer-friendly tools for threat modeling, code scanning, secrets detection, and dependency analysis. 3. Implement internal secure-by-default frameworks and reference architectures. [AI/ML Security]: 1. Collaborate with AI/ML teams to implement secure design patterns for model development, training pipelines, and service deployment. 2. Develop and enforce security controls for AI applications, including data integrity, robustness, governance, and prompt injection prevention. 3. Evaluate and integrate emerging tools for securing ML pipelines, generative AI models, and AI APIs. [Security Enablement, Education & Documentation]: 1. Build scalable security enablement programs, including secure coding workshops, bootcamps, and self-service resources/platforms. 2. Develop and maintain internal security documentation, policies, and standards. [Research & Continuous Improvement]: 1. Stay current on application security threats, AI security research, and best practices in cloud and software engineering.

Responsibilities • Run performance test in emulator and real-silicon • Collect and organize performance results • Update the provided test cases with instructions from the senior colleagues • Build test regression Minimum Qualifications • (Most important) Familiarity with Linux command line • (Most important) Familiarity with data visualization with Google Sheets or Microsoft Excel • (Most important) Familiarity with Git and Gerrit • Modify C source file parameters based on the given instructions • Basic knowledge of SoC topology • Arm interconnect (Booker-CI), AMBA AXI protocol Preferred Qualifications • In-depth knowledge of SoC and embedded system • CPU, Camera systems, Bus fabric, DMA • Familiarity with Continuous Integration and Jenkins • Familiarity with the use of Zebu emulator and Verdi • Familiarity with Little Kernel and Android GDB • Familiarity with Python programming GDB