[job description]
Wolley is seeking candidates for a digital design engineer position. You will join an experienced team designing next-generation memory, storage controllers, and high-speed interface standard.
You will also contribute to design concept discussion, architecture definition, as well as design implementation.
‧ Architecture design and RTL implementation
‧ System bus and related peripheral designs
‧ SoC and emulation platform design
‧ SoC system performance analysis
[Requirement]
1. Bachelor's or Master's degree in Electrical Engineering or related fields
2. Familiar with RTL design, SystemVerilog, front-end design flow
3. The following working knowledge is desired:
* Python programming
* TCL scripting
* Universal Verification Methodology (UVM)
* Low power design and analysis
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.內部學習平台提供超過4,000堂線上課程,其中包含近850堂資料科學、人工智慧、數據思維與程式技術等多元主題,支援彈性自主學習
.建立跨部門的 AI實作班與技術社群,定期舉辦研習與交流活動,讓知識轉化為實戰力
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【邀請您將104履歷同步上傳至華邦官方網站,將使您的履歷優先被主管看見】此職缺履歷登錄網址:https://bit.ly/4lHkbzD
[工作內容]
1. Responsible for design and development of digital ICs, including Verilog RTL coding, functional verification, and optimization.
2. Participate in the complete ASIC design flow: specification, RTL design, synthesis, static timing analysis, and physical design handoff.
3. Perform Design-for-Test (DFT) implementation, including scan insertion and MBIST, to support manufacturability and testability.
4. Support SoC integration, including bus protocols (AMBA) and high-speed interfaces (PCIe, SerDes).
1. 負責數位IC設計整合:
a. 依客戶需求設計整合IC功能、工作頻率、介面規格、消耗功率等基本規格
b. 完成SoC系統架構設計,並依功能單元運作屬性區分區塊規格
c. 使用Verilog/VHDL編程內部功能並撰寫RTL code
2. 負責功能驗證與除錯
a. 制定功能驗證計畫
b. 審核驗證計畫的完整性和正確性
c. 進行基本模擬,確認RTL code的功能
d. RTL code寫入FPGA晶片連接系統測試,驗證RTL code
3. 負責時序分析與功耗管理
a. 產出邏輯閘級電路連線網表(netlist)
b. 進行SoC系統的時序分析
c. 進行SoC系統的功耗分析
4. 其它主管交辦事項
【必要條件】
1. 電機、電子、資訊工程或相關科系,碩士以上學歷
2. 三年以上 SoC 設計或整合經驗
3. 熟悉CPU子系統設計整合
a. 熟悉 ARM 架構,
b. 對 RISC-V 架構有基本認識
4. 熟悉數位IC前端設計流程,如RTL design、Lint/CDC、Synthesis、STA、LEC、ECO等
5. 具類比IP整合相關經驗,例如PHY、Serdes、PLL等
6. 熟悉IC後段設計流程,如DFT、MBIST、P&R、post-cilicon system level debugging等
1. 具 0~2年數位晶片設計,或有 0~5年類比晶片設計工作經驗。
2. 具備基本數位和類比電路知識,熟習標準晶片設計流程。
3. 熟習業界常用EDA tools, 或Matlab/ Simulink。
4. 研習過CMOS or BiCMOS 類比設計電路課程,對放大器有基礎認識。
5. Experience in these areas is preferred:
* BiCMOS or CMOS high-speed (>20Gb/s) circuit, Linear electrical amplifier &
equalizer, High-speed (>25G) CDR/PLL/SerDes.
* Linear optical laser driver & receiver (TIA + linear amplifier)
本職位負責類比IC電路的設計、驗證和除錯。這是一個高度技術性的職位,對公司的產品開發至關重要。我們正在尋找一位熱愛類比IC設計並具有相關經驗的人才,以推動公司的技術創新和發展。
如果您對這個職位感興趣,請投遞您的履歷表,我們立即與您聯繫。
We are seeking a highly motivated Digital IC Design Engineer to join our dynamic team. The ideal candidate will have a strong background in digital design, a passion for innovation, and the ability to work collaboratively in a fast-paced environment.
1.Design and implement digital integrated circuits for low power MCU, including timing control, image processing, GPIO, and interface control.
2.Collaborate with cross-functional teams to define specifications and requirements.
3.Perform RTL design using VHDL/Verilog and simulation using tools such as ModelSim or VCS.
4.Conduct functional verification and validation of designs through simulation and formal methods.
5.Develop low power image processing and camera control algorithms, pipelines, and HW-friendly imaging technologies.
6.Hand on ISP block (AE, AWB, BPC, etc.) design and modification.
7.Optimize designs for performance, area, and power consumption.
8.Participate in design reviews and provide constructive feedback.
9.Assist in the integration and testing of digital systems.
10.Review technical literature, collect data, and specify solution options. Design, analyze, simulate, test, and document algorithm options.
11.Familiar with MIPI, I2C, serial, parallel output data control is plus.
12.Familiar with design flow and block integration is plus. (Required for manager)
13.Participate in system requirements definitions and schedule plan. ( Required for manager).
Preferred Qualifications:
1.Experience with low-power design techniques.
2.Knowledge of hardware description languages and electronic design automation (EDA) tools.
3.Familiarity with mixed-signal design concepts is a plus.