「EDA應用工程師_Application engineer」的相似工作

This vacancy is open for talent pool collection. We will contact you if we have proper vacancies that fit with your profile. Job Mission Represent manufacturing and act as gatekeeper from manufacturing to D&E function Add value in overall manufacturing processes such as forming, machining, joining, and assembling Job Description Contribute to the solution of faults and takes the necessary initiatives and practical decisions to ensure zero repeat Identify gaps and drive assigned process improvement projects and successful delivery Initiate and drive new procedure changes and projects Develop and maintain networks across several functional stakeholders Prioritize works and projects based on business situation Transfer knowledge and train colleagues on existing and newly introduced products Education Master degree in technical domain (e.g. electrical engineering, mechanical engineering, mechatronics) Experience 3-5 years working experience in design engineering Personal skills Show responsibility for the result of work Show proactive attitude and willing to take initiative Drive for continuous improvement Able to think outside of standard processes Able to work independently Able to co-work with different functional stakeholders Able to demonstrate leadership skills Able to work in a multi-disciplinary team within a high tech(proto) environment Able to think and act within general policies across department levels Diversity and inclusion ASML is an Equal Opportunity Employer that values and respects the importance of a diverse and inclusive workforce. It is the policy of the company to recruit, hire, train and promote persons in all job titles without regard to race, color, religion, sex, age, national origin, veteran status, disability, sexual orientation, or gender identity. We recognize that diversity and inclusion is a driving force in the success of our company. Need to know more about applying for a job at ASML? Read our frequently asked questions.

Please apply this role through https://careers.synopsys.com/job/hsinchu/r-and-d-engineering-sr-staff-engineer/44408/84900058096 Synopsys is looking for motivated Product Engineer to help design, develop and test state of the art Static Timing, Characterization and Library modelling tools. The primary focus of the Product Engineer is closely working with R&D team, to influence technologies/solution roadmaps and provide R&D team with accurate input from Field AEs, helping them focus on the most critical design challenges and help define solutions to critical problems. The engineer will work closely with Field AEs, ensuring overall consistency of end-to-end design and analysis flow to meet customer needs. The engineer will also work with Sales and Marketing teams to find and develop new markets, drive new tool evaluations and help customers with the adoption and continuous usage of Static Timing, Characterization and Library Modelling, thus enabling Chip Design customers achieve best Timing, Power and Characterization Goals. Synopsys’ existing and forthcoming tools offer an advanced transistor-level static timing characterization and library modelling solution that addresses the existing and emerging challenges in custom and memory design. They offer predictability and improved productivity to designers. Their concurrent timing, SI features and advanced variation aware analysis enables designers to accurately and quickly identify design issues early-on and avoid expensive late-finding of problems in silicon. Main responsibilities: • Drive new products and new product features that exceed customer needs. • Work with RnD to enable timely implementation of new products and features, and important bug fixes. • Provide consultation to prospective users and/or product capability assessment and validation. • Provide tool trainings to customers and Field AEs. • Provides technical expertise to sales staff through sales presentations and product demonstrations. • Assists the sales staff in assessing potential application of company products to meet customer needs and preparing detailed product specifications for the development and implementation of customer applications/solutions. Requirements: We are looking for an innovative, motivated, and dependable person, with at least BS degree and 8+ years of recent hands-on experience including: · Exceptional expertise in transistor-level analysis and debug circuit level issues for SRAM, RF, ROM memories and Standard Cells. · Good exposure to static timing concepts and CMOS engineering fundamentals. · Good knowledge of TCL and or other scripting languages. · Very good communication, social and leadership skills. Plus: · NanoTime or PrimeLib experience highly desirable.

1. 管理及維護Linux系統工作站。 2. 管理及維護EDA Tools。 3. IC設計流程開發、驗證及維護。

【本職缺優先審核至高通官網投遞人選】請至高通官網上傳英文履歷表https://careers.qualcomm.com/careers/job/446705989572 【Talents who apply job through Qualcomm Career Website will be reviewed and considered as top priority】 https://careers.qualcomm.com/careers/job/446705989572 【General Summary】 As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm CPU Engineer, you will lead innovative Central Processing Unit (CPU) design efforts that have a critical impact on industries across the world. Qualcomm Engineers collaborate with cross-functional teams to design, verify, and implement multi-core CPU operations for all Qualcomm Business Units. 【Roles and Responsibilities】 • Collaborate with cross-functional teams (RTL, Physical Design, Circuits, CAD) to address critical physical design challenges in CPU implementations. • Develop innovative techniques within Physical Design and optimization space to meet stringent PPA targets. • Coordinate with CPU Software, Architecture, and RTL teams to understand various CPU use cases and propose impactful PPA optimizations. • Engage with external CAD tool vendors and internal CAD teams to identify and enhance optimization issues related to CPU designs. • Partner with all block-level implementation teams to analyze, implement, and improve optimization methods relevant to the designs. • Partner with Process, SoC and Post-silicon teams to analyze, improve design implementations. 【Must have skill/experience】 • Experience with Synthesis, place and route and signoff timing/power analysis. • Knowledge of high performance and low power implementation techniques • Proficiency in scripting (TCL, Python, Perl) 【Minimum Qualifications】 • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 6+ years of Hardware Engineering, Electrical Engineering, or related work experience. OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 4+ years of Hardware Engineering, Electrical Engineering, or related work experience. OR PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field and 3+ years of Hardware Engineering, Electrical Engineering, or related work experience.

請務必投遞官網(12438): https://careers.synopsys.com/job/hsinchu/applications-engineering-staff-engineer-ic-validator/44408/84710683632 You Are: You are an innovative and resourceful engineer with a deep curiosity for solving complex technical challenges at the intersection of hardware and software. With a strong foundation in Electronic Engineering, Computer Science, or a related field, you are adept at leveraging your programming expertise—whether in Python, Tcl, Perl, or similar languages—to streamline and enhance engineering workflows. Your experience within UNIX/Linux environments equips you to navigate high-performance computing scenarios with ease. You thrive in collaborative, cross-functional teams and are energized by the opportunity to work closely with top-tier foundry partners and leading fabless companies. Your keen understanding of physical verification flows—such as DRC, LVS, PERC, FILL, and DFM—sets you apart, and you are eager to deepen your expertise in SoC physical design enablement, process effect analysis, and signoff. You are detail-oriented, capable of producing clear technical documentation, and communicate with clarity and empathy across diverse audiences. What You’ll Be Doing: 1.Delivering advanced physical verification solutions (DRC/LVS/PERC/Fill) for top-tier foundries and key fabless customers, ensuring high-quality silicon signoff. 2.Developing and validating process design kits (PDKs) and verification methodologies in collaboration with R&D and customer teams. 3.Partnering with R&D to innovate and improve Synopsys tools and flows, contributing to the evolution of physical verification technologies. 4.Providing hands-on customer support, troubleshooting issues, and delivering timely resolutions that enhance customer satisfaction and product adoption. 5.Coordinating with internal teams, including product managers and end-users, to align on best practices and ensure seamless integration of new technologies. 6.Documenting technical solutions, validation methods, and customer workflows for knowledge sharing and process improvement. 7.Staying up to date on industry trends and applying new insights to continuously optimize verification processes and tools. The Impact You Will Have: Accelerate the adoption and success of Synopsys physical verification products in leading-edge semiconductor manufacturing processes. Drive the development of robust PDKs and methodologies that enable customers to achieve first-time-right silicon. Enhance the quality and reliability of Synopsys verification tools through direct feedback and collaborative innovation with R&D teams. Strengthen Synopsys’ reputation as a trusted partner to top-tier foundries and fabless customers worldwide. Facilitate faster product cycles and reduced time-to-market for customers by delivering efficient and effective signoff solutions. What You’ll Need: BS or MS degree in Electronic Engineering, Computer Science, or a related field. Proficiency in at least one programming language, such as Python, Tcl, or Perl. Hands-on experience with UNIX/Linux environments and command-line tools. Familiarity with physical verification flows (DRC, LVS, PERC, FILL, DFM) and understanding of complex layout/electrical design rules. Strong investigative, analytical, and problem-solving abilities, with a passion for learning new technologies. Ability to produce clear, concise technical documentation and validation reports. Prior knowledge of tool/runset development/support and experience with SoC physical design is a plus.

Position Description: 1. To provide key technical support in digital IC design implementation product demonstration, and sales presentations. 2. To demonstrate strong ability and to be hands-on in full APR flow including floorplan, placement, timing analysis, CTS, signoff timing closure methodology. 3. To support key customer engagements on the business increase. 4. Have real design tape-out experience especially for advanced node design. 5. To play a leading role among other team members, while receive little instruction on routine and general assignments. Position Requirements: • Master with 10 years working experience or Bachelor with 12+ years’ experience in IC design. (Cadence Innovus experience will be a plus) • Understanding of full APR flow including timing, congestion analysis and low-power methodology. (Experience for Static Timing Analysis, including SI will be plus) • Good communication in English and Chinese, good confidence and good self-motivation. • Be familiar with shell/perl/tcl etc. script language.

【產品範疇】 Mobile/TCON - LCD display driver、OLED display driver Tablet - LCD display driver TV/NB -LCD display driver TCON 產品 【工作內容】 1.DRC/LVS Command file 撰寫&Maintain 2.Laker TF/UDD/PCELL 撰寫 3.PERC rule & 程式的開發 4.Analog design flow development 5.Shell/SKILL/TCL/Python 程式開發 6.新製程廠內的PDK development 7.In house Utility 開發 8.AI 輔助工具的開發與評估

(1)Must have BS in CS/EE of relevant experience in IC design field. (2)Familiar with IC design flow, placement and route (P&R), and layout. (3)Circuit knowledge and logic design relevant experience would be a plus.

Position Description: 1. To provide key technical support in digital IC design implementation, product demonstration, and sales presentations. 2. To demonstrate strong ability and to be hands-on in RTL-to-GDSII design methodology, including both challenging low power and high-performance designs. 3. Have real design experience including floorplan and partition, place, CTS, route, STA timing closure, Physical verification, RC extraction, Power Network analysis. 4. Assist in technical evaluation, assessment and delivery of concurrent ASIC/SoC designs. 5. To play a leading role among other team members, while receive little instruction on routine and general assignments. Position Requirements: 1. A bachelor's degree is essential and 3+ years’ experience in IC design, electronic engineering or computer science applications. 2. Ability to understand and articulate technical issues, (and knowledge of) design products and their applications. 3. Requires working knowledge of one or more programming languages, and effective communication and soft skills. 4. An MS degree and/or working experience in multi-nation IC design house/or familiar with EDI/Innovus product is a plus. 5. Good communication in English and good work attitude. 6. Be familiar with shell/Perl/Tcl etc. script language.

投遞網址: https://careers.synopsys.com/job/hsinchu/r-and-d-engineering-sr-engineer/44408/85652406272 You Are: You are an experienced and passionate engineer with a profound curiosity for technology and a strong drive to solve complex problems. With a background in Electrical Engineering, Computer Science, Mathematics, or Physics, you have spent at least a decade mastering your craft, specializing in the intersection of software development and circuit design. Your expertise in C++/C programming, combined with a deep understanding of data structures, algorithms, and circuit simulation, sets you apart as a technical leader. You are comfortable navigating both analog and digital domains, leveraging your circuit design knowledge to drive innovation in electronic design automation (EDA) solutions. What You’ll Be Doing: • Designing, developing, and optimizing SPICE circuit simulation engines to enhance performance and accuracy. • Collaborating with global R&D teams to implement new algorithms and features for circuit analysis and optimization. • Analyzing and resolving challenging functional and performance issues in circuit simulation software. • Providing expert customer support, addressing technical inquiries, and guiding users through complex simulation problems. • Interpreting customer requirements and translating them into technical solutions and product enhancements. • Preparing and delivering technical presentations and documentation to both internal stakeholders and external customers. • Staying current with emerging trends in EDA, circuit simulation, and semiconductor technology to inform product direction. The Impact You Will Have: • Drive continuous improvement in Synopsys’ circuit simulation tools, directly impacting the success of semiconductor innovations worldwide. • Enable customers to achieve faster, more accurate chip designs by delivering robust and reliable simulation solutions. • Enhance the scalability and usability of EDA products, supporting the design of next-generation electronics. • Foster strong customer relationships through exceptional technical support and solution delivery. • Contribute to a collaborative, high-performance R&D culture that values knowledge sharing and creative problem-solving. • Shape the roadmap of Synopsys’ industry-leading simulation technologies through your insights and expertise. What You’ll Need: • MS or PhD in Electrical Engineering, Computer Science, Mathematics, Physics, or a related field. • 10+ years of hands-on experience in software engineering or circuit design. • Strong proficiency in C++ and/or C, with a solid grasp of data structures and algorithms. • Deep understanding of analog and digital circuit design principles. • Proven ability to analyze and resolve complex software or hardware issues independently. • Excellent English communication skills, both written and verbal. Who You Are: • Analytical thinker with a systematic approach to troubleshooting and problem-solving. • Effective collaborator who thrives in diverse, multicultural teams. • Proactive communicator with strong presentation and interpersonal skills. • Adaptable and resilient in the face of technical challenges and evolving priorities. • Detail-oriented, with a passion for delivering high-quality, reliable solutions. • Customer-focused, with a commitment to understanding and meeting user needs. The Team You’ll Be A Part Of: You will join a dynamic and innovative R&D team dedicated to developing advanced SPICE circuit simulation software. Our team brings together experts in software engineering, circuit design, and EDA solutions, working collaboratively across continents to deliver cutting-edge products. We thrive on tackling complex engineering challenges and are committed to continuous learning, knowledge sharing, and supporting each other’s growth. Your contributions will directly influence the capabilities and success of Synopsys’ simulation tools, empowering customers around the world.

1. Responsible for SOC physical implementation including floorplan, power plan, physical synthesis, clock tree, routing, RC, STA, timing closure, EM/IR, DRC/LVS to GDS out. 2. Responsible for APR physical design flow development & automation

Job Description We are seeking a talented individual who will participate Virtuoso PDK (Process Design Kit ) development, quality and PDK applications related projects with leading foundry. This position will support Virtuoso PDK quality delivery, SKILL programming in task delivery, also provide PDK applications related support and interact with customers to overcome challenge in a fact-pace environment. Position Requirements: • MS degree in Electrical Engineering, Computer Engineering or similar areas. • Experience in analog design flow support or PDK delivery. • Knowledge and experience with analog design layout/simulation/digital/analog IC design flow, with layout domain knowledge would be a plus. • Experience in Linux shell environment and script programming, such as Perl and Tcl preferred. • Good communication skills in English. • Desire to learn, to take the challenge and to be a team player.

Job Description: This position is in Cadence Pegasus Physical Verification R&D team in Hsinchu, Taiwan. The candidate for this position will be developing design rule check (DRC) and FILL decks for advanced nodes of semiconductor manufacturing, The job involves creating quality check (QC) patterns, writing physical verification DRC and FILL rules and developing decks consisting of these rules. It also involves testing these decks on real customer designs and troubleshooting the deck and tool issues, providing feedback to Pegasus Foundry Team, Pegasus R&D, and foundry partners. Requirement: At least 2 years of previous experience with DRC or FILL deck development, and BS or MS degree in engineering.

1. 管理維護 Linux Server(Operation Server , Simulation Server, License Server) 2. 管理維護 EDA tools(Synopsys, Cadence, Siemens, others) (Front End/Back End/Verification) 3. User 相關需求處理 4. EDA自動化流程系統維護及程式開發

[駐點於知名科技公司服務] 希望你對最新科技技術和EDA工具有強烈的學習熱情，並且願意參與從SYN、APR、signoff到Foundation IP最新技術的開發，將這些技術應用到最前沿的產品中。 1. 設計流程維護： 維護和優化CAD參考流程，助力IC設計。 確保設計流程性能和準確性達到最佳狀態，產出更優質的成果。 2. 工具整合： 整合各種EDA工具（如Synopsys、Cadence、Mentor Graphics）到參考設計流程中。 確保不同工具之間的相容性和無縫操作，提升工作效率。 3. 文件編寫: 創建和維護參考流程的全面文件。 詳細記錄所有更改和更新，方便用戶未來參考。 4. 性能監控： 監控參考流程的性能，識別改進區域。 實施增強措施，提高流程效率，縮短設計週期時間。

1. 了解 Mentor Graphics EDA PADS, Expidition, Hyperlynx 軟體產品尤佳，包括其功能、 優點和應用。 2. 與銷售團隊合作，了解客戶需求並在售前活動期間提供技術支援。 3. 客戶教育訓練課程，提供客戶在工具使用上之必要協助。 4. 提供客戶正確的產品規格與應用相關資訊，以作為客戶設計產品時的參考依據。 5. 提供客戶偵錯服務與技術支援，以協助發現並解決產品試產時所發生的問題。 6. 根據客戶互動期間收集的客戶見解和技術要求，監控市場趨勢、競爭對手活動和客戶回 饋，以確定產品改進和增強的機會，向產品開發團隊提供回饋。 7. 建立技術文件、教學課程和最佳實務指南，幫助客戶發揮軟體價值；同時亦可為銷售團隊 成員舉辦內部培訓課程，以提高他們的產品知識。 8. 不定期至原廠受訓，提升技術能力。

ASIC Physical / Backend Designer 將負責數位電路的後端實體設計，包括規劃與優化晶片的布局（Floorplan）、電源網格設計（Power Grid Design）、自動布局與繞線（Place and Route）、時脈樹合成（Clock Tree Synthesis）、靜態時序分析（Static Timing Analysis, STA）、物理驗證（Physical Verification）等工作。 主要職責 1. 熟悉以下製程：22nm,16/12nm, 7/5nm Automotive process及其Signoff Criteria. 2. 晶片布局設計：根據Design Specification, Pin Table, Netlist，執行Floorplan規劃及設計。 3. 熟悉Safety Specification Format (SSF)及其實作流程。 4. 時序分析和優化：進行靜態時序分析，熟悉CTS相關技術，確保晶片具備必要的性能，並解決潛在的Timing Violations. 5. 電源架構規劃：熟悉UPF流程，具備Multi-Voltage設計經驗。 6. 功耗分析及優化：熟悉IR分析流程，進行Power Grid優化以符合設計要求。 7. 面積優化：在滿足設計約束條件的前提下，優化晶片布局以達到最小化面積目標。 8. 設計驗證：執行物理驗證(PV)工作，包括DRC（設計規則檢查）、LVS（佈局與網表檢查）等，確保設計符合製造要求。 9. 了解製造相關流程，包括封裝設計和製造約束條件。 10. 與團隊協作：與前/中端設計工程師、製造工程師及測試團隊緊密合作，確保設計符合需求。

At cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. You’ll develop state-of-the-art library characterization tools for our worldwide customers in an exciting and innovative environment. Position Responsibilities:  Full time in industry leading software development  Involvement in local customer engagements in cooperation with global teams  Develop new product features, including invention, design and implementation new algorithms to build industry leading products Desired Qualifications:  Experiences in EDA/IC industry  Experiences in library characterization, spice simulation, or transistor level timing  Effective communication skills, passion to drive a project and to win customers Additional Job Description  Experience in developing library characterization or circuit simulation software  High level understanding of SPICE simulation transistor models  Experience with distributed programming, database design, and cloud APIs for distributed computing  Proficiency designing data structures, algorithms, and software engineering principles  Experience in developing Machine Learning technology and deploy it at customers

大塚是一家充滿活力、穩步成長的公司，歡迎在這裡找到屬於自己的舞台！ ●2008年10月股票掛牌上櫃 (股票代號3570) ●連續四年營收超越10億元 ●薪資水平在上櫃公司同業中名列前五名 ●擁有最完整的技術能量，每年客戶群超過2000家以上 ●是台灣產業涵蓋最廣的繪圖軟體解決方案代理商 ⭕ 工作內容 1. 協助專案規劃執行╱追蹤╱管理。 2. 電腦輔助設計軟體操作經驗及概念。 3. 產品線教育訓練與技術文件製作。 4. 協助客戶問題處理。 5. 其他主管交辦事項 ⭕ 需求條件 1. 機械相關科系畢（無經驗可，公司提供完善培訓） 2. 具1年以上CAD實務經驗。 ⭕ 其他資訊 1. 薪資福利：依學、經歷面議核薪。 2. 上班時間：固定日班08:30-17:30 (含午休時間，彈性上下班30分)。 3. 依據公司經營狀況發放季獎金、年中分紅、年終獎金及員工酬勞等。

Job description: Validate HDL debug tools, test automatically script handling and help customers to clarify issues, even find workaround solutions. Requirement: 1. MS degree or above with EE or CS background 2. Understand Verilog/VHDL or has 2+ years-experience in HDL design. 3. The experience of HDL simulator/debug tool verification is plus. 4. Familiar with Linux environment or scripts.