1. 針對高速介面進行信號完整性模擬。
SI simulation : TDR, S parameter,Eye diagram,Crosstalk..
2. 電路板電源完整性模擬。
PI simulation : IR Drop , PDN..
3. 對於佈局圖給予改良建議。
Polar應用及評估PCB & VNA材料選擇方式
4. 信號完整性異常除錯。
1.Develop & build SSD validation flow & test plan.
2. Discuss directly with customers for qualification process & test plan
3. Reproduce customer issues, triage failures, & verify fixes with the project team
4. Working closely with the project team to develop test scripts to fulfill customers' requirement
5. Design & optimized the manufacturing framework
6. Manage internal qualification schedule & reports
7.Go on-site for JQ testing