「MEMS電子研發工程師」的相似工作

1.進行 MEMS 元件結構設計與模擬 (COMSOL / ANSYS / CoventorWare)。 2.分析應力、共振頻率、致動行為，並優化設計。 3.與製程工程師合作，進行設計驗證與樣品測試。 4.撰寫設計文件，協助可靠度驗證與改良。 我們誠摯邀請充滿熱情且經驗豐富的MEMS製程工程師加入領先業界的團隊！如果您對半導體及微機電有深厚知識，渴望投入尖端技術開發、追求卓越產品良率與效率，歡迎與我們一起開創未來！

This vacancy is open for talent pool collection. We will contact you if we have proper vacancies that fit with your profile. Job Mission Represent manufacturing and act as gatekeeper from manufacturing to D&E function Add value in overall manufacturing processes such as forming, machining, joining, and assembling Job Description Contribute to the solution of faults and takes the necessary initiatives and practical decisions to ensure zero repeat Identify gaps and drive assigned process improvement projects and successful delivery Initiate and drive new procedure changes and projects Develop and maintain networks across several functional stakeholders Prioritize works and projects based on business situation Transfer knowledge and train colleagues on existing and newly introduced products Education Master degree in technical domain (e.g. electrical engineering, mechanical engineering, mechatronics) Experience 3-5 years working experience in design engineering Personal skills Show responsibility for the result of work Show proactive attitude and willing to take initiative Drive for continuous improvement Able to think outside of standard processes Able to work independently Able to co-work with different functional stakeholders Able to demonstrate leadership skills Able to work in a multi-disciplinary team within a high tech(proto) environment Able to think and act within general policies across department levels Diversity and inclusion ASML is an Equal Opportunity Employer that values and respects the importance of a diverse and inclusive workforce. It is the policy of the company to recruit, hire, train and promote persons in all job titles without regard to race, color, religion, sex, age, national origin, veteran status, disability, sexual orientation, or gender identity. We recognize that diversity and inclusion is a driving force in the success of our company. Need to know more about applying for a job at ASML? Read our frequently asked questions.

1.負責 MEMS 元件製程開發與製作（黃光微影、薄膜沉積、乾蝕刻、晶圓鍵合等）。 2.與設計工程師合作，根據模擬設計導入量產製程。 3.分析與改善製程良率，提出製程優化方案。 4.協助進行樣品測試、失效分析與可靠度驗證。 我們誠摯邀請充滿熱情且經驗豐富的MEMS製程工程師加入領先業界的團隊！如果您對半導體及微機電有深厚知識，渴望投入尖端技術開發、追求卓越產品良率與效率，歡迎與我們一起開創未來！

1.支援客戶由開發至量產所遇到的各種WiFi相關軟、硬體問題； 2.協同業務作業，針對客⼾需求訪談、分析以及可⾏性⽅案建議； 3 提供客⼾端技術問題解決與回饋，協助客⼾完成產品及RF芯片調測等

1. 專案管理：開發與生產各項進度跟催與協調 2. 訂單管理 3. 產品文案設計 4. Forecast 管理 5. APQP跨部門溝通協作 6. 其他主管交辦事項

• 客戶專案導入與技術問題排除 • 跨平台Sensor驅動程式支援 • 售後服務與技術支援，包含Sensor IC與Module • 產品功能驗證與測試 • 技術文件撰寫與維護

對 FPGA design, Ethernet switch, MPLS, 光纖傳輸, VoIP等相關通訊產品有專長或興趣者。 1、指導工程師完成專案 2、電路規劃設計 3、系統整合驗證

Job Title: NPU Modeling Engineer Job Description: Overview: We are seeking an experienced NPU Architect to join our team. As an NPU Architect, you will play a crucial role in designing and implementing the hardware model for our Neural Processing Unit. Your expertise will be instrumental in ensuring efficient and accurate execution of neural network workloads on our NPU. Responsibilities: 1. NPU Architecture Design: • Collaborate with cross-functional teams to define the architecture and specifications for the NPU. • Design the NPU's core components, including the PE array, memory hierarchy, and control logic. • Optimize for performance, power efficiency, and scalability. 2. Bit-True Hardware Model Implementation: • Develop a bit-true hardware model of the NPU in C language. • Ensure that the model accurately represents the NPU's behavior, including arithmetic operations, memory access, and control flow. • Validate the model against reference neural network workloads. 3. Cycle-Accurate Modeling: • Create a cycle-accurate model of the NPU to simulate its behavior at the clock cycle level. • Account for pipeline stages, data dependencies, and timing constraints. • Use tools like Verilog, system-Verilog, or specialized simulation environments to achieve cycle-accurate modeling. 4. Performance Analysis and Optimization: • Profile the NPU model to identify bottlenecks and areas for improvement. • Propose and implement optimizations to enhance performance and reduce latency. • Collaborate with software teams to fine-tune the NPU's behavior. 5. Verification and Validation: • Create testbenches and test vectors to validate both the bit-true and cycle-accurate models. • Conduct functional and performance testing to ensure correctness and compliance with specifications. • Debug and resolve any discrepancies between the models and the actual NPU. 6. Documentation and Communication: • Document the NPU architecture, design decisions, and implementation details. • Present findings, progress, and challenges to stakeholders and management. • Collaborate with software engineers, firmware developers, and system architects. Qualifications: • Master's or Ph.D. degree in Electrical Engineering, Computer Science, or a related field. • Minimum of 3 years of experience in NPU architecture design and implementation. • Proficiency in C/C++/Verilog/System-Verilog programming for hardware modeling. • Familiarity with systolic arrays, matrix multiplication, and neural network accelerators. • Knowledge of bit-true modeling, fixed-point arithmetic, and floating-point arithmetic. • Experience with verification tools and simulation environments. • Strong analytical and problem-solving skills. • Excellent communication and teamwork abilities. • Attention to detail and commitment to quality. If you are passionate about NPU architecture, hardware modeling, and want to be part of a team driving innovation, we encourage you to apply. Join us in shaping the future of AI!

1.CAD 3D 操作與建模 需具備 CAD 3D 軟體操作經驗（例如：SolidWorks、AutoCAD、IronCAD 等） *公司提供原廠技術支援，幫助你快速熟悉與進階使用 2.現場量測與實作 實地至台積電進行管路尺寸與空間量測工作 熟悉現場作業安全規範尤佳（無經驗可由團隊協助指導） 3.產品開發與技術學習 協助團隊進行新產品開發與測試 可逐步接觸專利設計、製造轉換、性能評估等工作內容 4.熱忱學習、勇於挑戰 歡迎主動學習、自我驅動型人才加入 我們重視你的成長，也樂意提供各類技術培訓與學習資源 【加分條件】 有設備組裝、氣體/真空系統、感測器應用等相關經驗者佳 曾接觸無塵室作業、工安訓練者加分 具電機、機械、材料、化工背景尤佳

1.產品電性量測與分析、資料撰寫。 2.熟悉POWER SUPPLIER、POWERMETER、示波器等基本設備、架設量測電路。 3.主管交辦事項 ▲ 本職缺依(個人專業)及(學經歷、技能、潛力)核定職務及敘薪。 ▲【該部門屬彈性工時，彈性上下班1小時，每日工作總時數8H】

1.網通Embedded System(嵌入式系統)產品開發。 2.產品驗證、測試和改進處理技術問題和故障排除。 3.WiFi、Celluar與Ethernet、Switch等網通設備開發。 4.跨部門團隊合作，問題解決及協調。 5.產品安規測試。

【職務說明】 我們是一條以AI 驅動的先進封裝產線，專注於 MicroLED 與 VCSEL 的巨量轉移、檢測與修補，致力於打造下一世代的 先進顯示技術與矽光子應用。我們正在尋找一位具備頂尖 AI 專業與智慧製造導入經驗的領導者，帶領團隊建構以資料為核心的決策平台，全面提升製程效率、良率與品質穩定性，加速 AI 技術在封裝產線中的實際落地與規模化應用。 【工作內容】 1. 制定 AI 導入策略，聚焦於 MicroLED / VCSEL 巨量轉移、瑕疵檢測、重工修補與製程參數最佳化等核心環節。 2. 領導資料科學家、AI/ML 工程師與軟體開發團隊，推動跨部門 AI 研發與部署。 3. 深度解析封裝產線之異質數據（如機台 log、SPC、AOI 影像、MES 資訊），建構可解釋性高的分析架構。 4. 開發高效能之缺陷分類、良率預測、自動瑕疵標註、根因分析模型，並落地於產線即時應用。 5. 應用強化學習於巨量轉移製程參數之動態調整與優化，突破微組件對位與轉移良率瓶頸。 6. 導入大型語言模型（LLM）與視覺語言模型（VLM），應用於智慧良率歸因、報表生成與製程決策輔助。 7. 建立並優化 MLOps 架構與模型版本管理系統，支援模型從研發到部署的全生命週期。 8. 推動公司內部 AI 能力建設，協助夥伴部門建立資料思維與基本技術知識。 9. 與製造、測試、IT、設備等部門緊密協作，確保模型輸出能轉化為實際效益。 Job Description: We are seeking a visionary leader with top-tier expertise in Artificial Intelligence and a proven track record in smart manufacturing implementation. In this role, you will lead the development of a data-driven intelligent manufacturing decision platform focused on MicroLED process optimization, production efficiency, yield maximization, and automated quality assurance. You will be responsible for the strategic planning of AI technology integration, cross-functional collaboration, advanced model development and deployment, and ensuring the successful adoption of AI innovations that significantly enhance manufacturing performance and product quality. Key Responsibilities: 1.Formulate AI strategies and roadmaps for MicroLED smart manufacturing, driving cutting-edge research, project planning, and prioritization. 2.Lead and develop a multidisciplinary AI team, including data scientists, AI/ML engineers, and software developers. 3.Perform in-depth analysis and mining of complex production data (e.g., equipment logs, sensor data, SPC, MES systems) to uncover deep insights and correlations. 4.Spearhead the development and optimization of advanced machine learning and deep learning models for defect detection, automated quality control, anomaly prediction, and root cause analysis. 5.Drive intelligent process optimization for key manufacturing steps (e.g., mass transfer) using advanced algorithms such as reinforcement learning to achieve dynamic parameter tuning and breakthrough efficiency gains. 6.Explore and implement applications of large language models (LLMs) and vision-language models (VLMs) for yield analysis, process knowledge extraction, and decision-making support. 7.Plan and implement efficient MLOps systems and lifecycle management for AI models. 8.Build internal AI capabilities and promote cross-functional AI thinking through education and training initiatives. 9.Collaborate closely with manufacturing, equipment, IT, and quality departments to ensure successful deployment and realization of AI solutions on the production floor.

工作內容： 1. 熟悉硬體電路，PCB元件組焊能力 2. 制定各項產品測試計畫及建立測試SOP 3. 進行Bug重現，協助開發團隊分析與釐清問題 4. 撰寫及分析產品各項測試報告 5. 誠信負責，願意學習成長，主動積極解決問題

1.電路圖設計與檢視 2.PCB Layout設計與檢視 3.系統驗證與除錯(Debug) 4.依據客戶需求,設計硬體架構 5.依據產品特性,規劃以及施行適當的測試項目 6.配合工作團隊,將產品順利導入量產 7.熟悉工控產品設備

⚠️特別說明：此職位需on-site在新竹清大創新育成中心辦公室，無提供遠端工作條件。 ✅主要職責： 1. 高效能記憶體子系統（DDR/LPDDR Subsystem）之整合、開發與驗證。 2. 參與GenAI SoC設計，包括架構規劃、RTL設計、模擬與驗證。 3. 配合後端設計團隊，進行時序分析與設計優化。 5. 進行設計文件撰寫與維護，確保設計過程符合公司開發流程。 6. 針對客戶需求，進行系統分析與客製化設計開發。 ✅基本要求： 1. 電機、電子、資訊工程相關科系畢業，學士以上學歷。 2. 具備5年以上數位IC設計經驗。 3. 熟悉 DDR PHY 架構、控制器、timing calibration與 training 流程 4. 熟悉SoC Bus Fabric設計，具備AXI、AHB等匯流排介面經驗。 5. 熟悉RTL設計 (Verilog / System Verilog)。 6. 了解前端設計流程，包括模擬、合成、時序分析等。 7. 良好的問題分析能力，具備團隊合作精神。 ✅加分條件： 1. 有參與過 LPDDR Subsystem Integration與Silicon Tape-out 並成功量產 2. 熟悉 Synopsys LPDDR、Cadence GDDR IP/Subsystem 3. 熟悉 UPF、低功耗設計流程 4. 熟悉 DFT 、Scan、BIST ✅ Why Join Us 1. 與頂尖技術團隊共事，參與高效能 AI/高速記憶體解決方案開發 2. 自主創新文化，提供技術發揮與產品影響力兼具的工作環境

1.Probe Card電路板設計相關電路繪製。 2.Probe Card電路板設計相關零件佈局與線路佈線監督review. 3.整合並改進Layout and PCB simulation. 4.RF設計。

* 主要工作 - Load Board / Probe Card / Substrate PCB Layout 1. 熟悉Allegro 2. 有Load Board / Probe Card / Substrate PCB Layout 設計開發經驗者 3. 能與客戶端溝通並了解需求 ***將不定期到韓國總部接受訓練,提升專業技能!

Job Description UltraSense Systems is looking for an experienced and skilled Device Qualification and Reliability Engineering leader for the manufacturing organisation. The role requires both strong technical and a track record of success. You should be comfortable in driving product/device and package qualification and reliability stress testing in order to meet AECQ100 Grade 2 complaincy. You will work closely with customer Engineering to address customer quality issues from yield to reliability by driving “0 PPM”. Responsibilities o Work closely with multi-functional engineering groups and third parties to lead qualification of new products/devices with high quality. Establish plans and manage deliverables. o Drive investigation and resolution on qualification fallouts and product and process nonconformance of MRB, RMA events through means of FA, CAR, 8D, and reporting o Manage customer failure root cause analysis and 8D reporting o Drive Design for Reliability and Design for Test to ensure stress-ability and testability o Lead all aspects of and ensure adequate preparation for qualification including such as corner skew material, BIB/Socket, waveform, electrical bias, thermal effect, lifetime estimation o Perform FAI to ensure critical goals are reviewed before engineering, pre-production and production release for Product Manufacturing o Manage new product/device reliability testing and qualification such as TCT, HAST, and HTOL. o Drive investigation and resolution on qualification fallouts and product and process nonconformance of MRB, RMA events through means of FA, CAR, 8D, and reporting o Evaluate and perform Reliability Risk Assessment o Support PCN or ECN activities Qualifications o BS in EE or Pysics. MS or PhD preferred. >5 Years of relevant industry experience o Silicon engineering experience in the Device/Reliability from multinational companies o Outstanding communication skills required o Experience of silicon product level reliability qualification and lifetime behavior model o Board Level Reliability knowledge preferred o Expertise and working knowledge of commercial and automotive reliability standards (JEDEC, AEC) o Knowledge of reliability stress and test methods, failure mechanism acceleration models. o Good social and communications skills - comfortable working in multicultural teams. o Familiarity with IC components reliability failure modes, mechanisms, and failure analysis techniques preferred

1.Conduct feasibility studies before product kick-off. 2.Coordinate with the R&D team and other related teams. 3.Check new technology/design rules. 4.Manage new product development. 5.Prepare product samples for testing. 6.Perform competition analysis.

1. 負責管理研發團隊完成專案開發及交付。 2. 負責定期review各專案進度，分配適當研發資源滿足客戶交付時程。 3. 負責梳理各項核心技術與新技術調研，定期輸出技術開發road map。 4. 負責各項研發專利研擬與輸出。