「FPGA 資深工程師」的相似工作

The Staff/Sr. Engineer, CPLD will be based in Taiwan Taipei Wugu Site. The Staff/Sr. Engineer, CPLD performs the responsibility for CPLD programming and validation in Server/Storage Projects request. What a typical day looks like: 1. Skilled FPGA/CPLD Design Engineer with strong capabilities in Server/Storage system and hardware-level design. 2. Responsible for development and integration of CPLD/FPGA that implement functionality on prototypes: spanning from low-level hardware sequence control, logic control & status for embedded systems, to high-speed links, to high level IP blocks, to custom hardware-accelerated algorithms & filters. 3. Work closely with Hardware, BIOS, BMC and Firmware team for CPLD/FPGA development. 4. Designing validation plan and development spec. 5. Debugging platform and systems issues. The experience we are looking to add to our team: 1. 3-10 years of working experience in Firmware development. 2. Familiar in Verilog RTL language. Experienced with CPLD/FPGA development on Lattice, Altera and Xilinx devices. 3. Experience with I2C, SPI, LPC, UART, PCIe protocol design 4. Experience with verification methodologies, RTL and gate level simulations and debug. 5.Good problem-solving skills. The information we collect: We may collect personal information that you choose to submit to us through the Website or otherwise provide to us. This may include your contact details; information provided in online questionnaires, feedback forms, or applications for employment; and information you provide such as CV/Resume. We will use your information for legitimate business purposes such as responding to comments or queries or answering questions; progressing applications for employment; allowing you to choose to share web content with others or; where you represent one of our customers or suppliers, administering the business relationship with that customer or supplier.

1. CPLD/FPGA 經驗 Verilog、VHDL 程式編輯經驗 2. X86 ARM 架構 CPLD 設計經驗 3. 硬體設計架構系統規劃 4. 獨立專案作業能力佳 5. Module code 組織編輯能力 *歡迎對verilog coding有興趣者投遞，公司將依學經歷、能力核敘

【Responsibilities】 • Perform FPGA bitfile generation including synthesis, implementation, timing analysis, and bitstream creation • Conduct FPGA programming and board-level bring-up on target hardware • Support hardware verification, debugging, and validation on FPGA platforms • Assist with resource planning, timing closure, and FPGA design constraint management • Prepare technical documentation, test procedures, and maintain configuration/version control • Collaborate with cross-functional teams to ensure smooth product integration and functionality 【Required Qualifications】 • Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related fields • Familiarity with FPGA development flow including simulation, synthesis, implementation, and bitfile generation • Hands-on experience in creating and programming bitfiles for platforms using Xilinx, Intel, or Lattice FPGAs • Strong analytical and problem-solving skills, with a proactive learning attitude • Good teamwork and communication skills, especially for global cross-team collaboration • Ability to read and understand technical documents in English 【Plus Skills】 • Proficiency with tools like Xilinx Vivado, Intel Quartus Prime, or Lattice Diamond • Experience with hardware validation using oscilloscopes, logic analyzers, or protocol analyzers • Familiarity with high-speed interfaces such as PCIe, NAND Flash, DDR • Background in SSD controller integration or related FPGA-based systems • Programming experience in Python or C for automated test or scripting

1.制定 FPGA 設計需求/架構/協議/資源分配。 2.使用 VHDL/Verilog 進行電路設計/實現/模擬。 3.建立 Testbench：制定驗證計畫與測試案例。 4.執行功能驗證與系統測試、除錯與問題分析。 5.撰寫所設計之相關技術文件。

1. SOC/IP 整合工作，從RTL到 Netlist 2. clock tree structure design 3. Lint / CDC check / Synthesis/ DFT/ LEC

Digital designer with knowledge of embedded micro SOC developments and capability of carry a design from concept to production. The candidate should be skilled with hardware description language, formal verification methodology, logic synthesis, and timing closure. Knowledge of back-end design and experience of work closely with physical designer to complete place & route and meet power & timing contains are highly desirable. Project management skill is a plus. The senior candidate with ARM design platform experience and familiar with 55/40 nm MCMM implementation design flow as well as PPA analysis is a big plus.

(1) FPGA軟硬體開發 (2) Verilog程式開發 (3) 軟硬體除錯

1.具FPGA平台開發相關經驗 2.熟Verilog 3.熟顯示器TCON/Driver驅動原理者佳 4.能獨立建立FPGA開發環境平台 5.有數位邏輯IC開發經驗者佳

【About Us】 VICI Holdings' Hardware team is seeking a Senior Digital Design Engineer to join our dynamic group. In this role, you will be pivotal in advancing our trading systems, contributing to the development and enhancement of cutting-edge technologies. We boast the leading digital hardware development team in Taiwan and possess FPGA design technology in parallel with wall street trading firms. This expertise enables us to build ultra-low-latency, fully automated trading systems. Our trading strategies cover stocks, futures, and derivatives, achieving a daily global trading volume in the hundreds of millions dollars. 【Roles/ Responsibilities】 • Micro-architecture, design and implement high-performance digital circuits optimized for low-latency application • Develop high speed data paths, ensuring minimal logic depth and efficient pipeline • Optimize critical paths and combinational logic to reduce propagation delays and improve throughput • Work with Verilog/ SystemVerilog to implement RTL design • Apply parallelism and resource sharing techniques to enhance performance and throughput • Develop latency-aware micro-architectures for real-time processing and networking applications • Debug, optimize and iterate on designs using FPGA platform and cycle-accurate simulation • Work closely with digital/system verification engineers to ensure functional correctness and performance validation • Take ownership of FPGA verification tasks to ensure design correctness and performance. • Develop and execute verification plans for high-speed IPs such as PCIe, Ethernet, and Switches. • Support system validation engineer to debug FPGA issue Design Collaboration: • Collaborate closely with Algorithm, software, design validation and application team to define micro-architecture Performance Analysis: • Conduct performance testing and analysis, ensuring the low-latency goals are met across various use cases. • Capability to solve routing timing issue and analysis FPGA timing report result. 【Candidate Requirements】 • Master’s degree or above in EE, CE, or CS, plus 3–8 years of high-speed digital-design experience • Hands-on experience in IP-level digital-circuit design or IP integration (preferred) • Proficient in debugging and optimization with VCS and Verdi simulation tools • Comfortable working in Linux/Unix environments • Strong analytical and problem-solving skills with a performance-driven mindset 【Other Requirements】 • Proven ability to solve complex design challenges and deliver robust solutions • Experience designing ultra-low-latency data paths—arithmetic units, multiplexers, FIFOs, registers—for high-performance applications (preferred) • Familiarity with FPGA verification tools such as Quartus or Vivado (a plus) • Knowledge of high-bandwidth memory interfaces (DDR, HBM, etc.) • Understanding of networking protocols (Ethernet, PCIe, etc.) 【Interview Process】 • Resume Screening → HR Phone Screen → Face-to-Face Interview (with 30-60mins on-site coding test)

⚠️特別說明：此職位需on-site在新竹清大創新育成中心辦公室，無提供遠端工作條件。 ✅About the job • 負責數位IC設計的功能驗證，確保設計符合規格要求。 • 建立UVM驗證平台，撰寫測試案例，進行模組與整合驗證。 • 熟悉AMBA (AXI/AHB/APB) 匯流排協定，應用於驗證環境。 • 使用C語言或SystemVerilog撰寫測試程式，進行功能覆蓋率分析與除錯。 • 與設計團隊，協同解決設計問題。 • 參與測試計畫制定、驗證策略設計及驗證報告撰寫。 ✅基本要求： • 電機、電子、資訊工程相關科系畢業，學士以上學歷。 • 具備3-5年數位IC設計驗證經驗。 • 熟悉AMBA (AXI/AHB/APB) 匯流排協定。 • 熟悉UVM驗證方法學，具備搭建UVM平台經驗。 • 熟悉SystemVerilog或C語言，能撰寫驗證測試程式。 • 熟悉模擬工具 (如VCS、NC-Verilog、ModelSim等)。 • 良好的問題分析與解決能力，具備團隊合作精神。 ✅加分條件： • 具備SoC驗證經驗。 • 熟悉FPGA驗證流程或原型驗證經驗。 • 熟悉低功耗驗證或性能分析經驗。 • 具備腳本開發能力 (Perl、Python、TCL等)。 ✅需具備技能： • AMBA (AXI/AHB/APB) Protocol • UVM驗證方法學(必要) • System Verilog / C 語言 • 功能驗證平台建置 • 模擬工具使用 (VCS / NC-Verilog / ModelSim 等) • 問題分析與除錯能力 • 驗證策略與覆蓋率分析

振生半導體股份有限公司 (Jmem tek) 專注於半導體相關矽智財，提供設計服務與硬體資安專利，保護硬體資訊安全。如果您希望參與一個充滿潛力和創造力的環境，歡迎您加入我們的團隊。 工作內容： 1.負責 IP 介面控制與時序邏輯設計。 2.參與晶片上層模組連線與系統整合。 3.使用 Verilog 撰寫 RTL 並執行模擬與功能驗證。 4.使用 FPGA 平台進行原型驗證與軟硬整合測試。 5.執行 ASIC 合成流程，包括 DFT、Multi-Clock Domain 處理與 Timing Closure。 6.配合後段工程團隊完成實體設計整合與 Tape-out。 7.參與或主導加解密 IP 模組（如 AES、SHA、RSA、TRNG、PUF、PQC 等）之 RTL 設計與 SoC 整合。 8.協助規劃與實現整體 Security Architecture，包括安全啟動、安全儲存與通訊保護等功能。 9.撰寫與維護相關設計文件、整合驗證報告與安全模組測試報告。 10.直接帶領並管理約 3 位數位設計工程師，負責任務分配、進度追蹤與技術指導。 您需要具備的條件： 1.電子、電機、資工等相關科系碩士畢業，具備相關經驗者佳。 2.熟悉 ASIC 設計與開發流程，具 RTL-to-GDS 流程操作經驗。 3.熟悉 Verilog/SystemVerilog，並具備 Synthesis、Formal Verification、STA、FPGA 驗證等技能。 4.熟悉 AMBA 架構（AXI、AHB、APB）與常見 IP 介面整合。 5.具備 Tape-out 與量產經驗者佳。 6.具備低功耗設計經驗（Low Power / UPF）者佳。 7.具備 ARM 或 RISC-V MCU 系統開發與整合經驗者佳。 8.具備資安相關硬體設計經驗，熟悉加解密演算法（AES、RSA、SHA、PUF、PQC 等）與 Security Architecture 概念。 9.具備團隊管理經驗，能協助新人訓練、技術審查與跨部門協調者尤佳。 相關報導： 2025 國家科學及技術委員會舉辦「AI創新應用論壇暨IC Taiwan Grand Challenge頒獎典禮」 獲優秀團隊獎 https://ynews.page.link/xzLbF 2025 台灣最大AI競賽「智慧創新大賞」經濟部智慧創新大賞 IC新創及中小企業奪得「 金獎」 https://news.m.pchome.com.tw/living/twpowernews/20250503/index-17462668050674847009.html 量子電腦資安攻防戰！振生半導體首創PUF+PQC市場唯一最佳解方https://udn.com/news/story/7240/7917935 EE TIMES 報導：振生半導體引領IC安全創新 https://www.eettaiwan.com/videos/jmem-technology-leads-ic-security-innovation/ 2024 台灣新創世界杯「振生半導體奪冠」　10月赴美爭百萬美元投資款 https://finance.ettoday.net/news/2786606

1. PCIe /SATA /SD /eMMC /UFS /SAS controller firmware design 2. FTL (Flash Transfer Layer) algorithm design 3. PCIe/NVMe storage interface design. 4. CPU/OS/Simulator design or implementation 5. FCL(Flash Command Layer) design

- Experience with memory controllers (e.g. DDR DRAM, eMMC and other flash, etc.) - Experience in CPU or various buses (AXI, etc) - Good verilog writing skills - Willingness to work with a variety of tasks

Design CPU functional units. Responsibilities  Defining micro-architecture of the functional units  Writing RTL codes of the functional units  Writing documents of the function units  Working with cross-division teams to resolve functional, performance, power, and frequency issues related to the functional units Qualifications  3+ years of recent experience with Verilog logic design  Knows CPU micro-architecture, e.g. instructions, pipeline, caches, MMU  Knows power consumption of digital circuits  Good communicator in verbal and writing in English

Job Title: NPU Modeling Engineer Job Description: Overview: We are seeking an experienced NPU Architect to join our team. As an NPU Architect, you will play a crucial role in designing and implementing the hardware model for our Neural Processing Unit. Your expertise will be instrumental in ensuring efficient and accurate execution of neural network workloads on our NPU. Responsibilities: 1. NPU Architecture Design: • Collaborate with cross-functional teams to define the architecture and specifications for the NPU. • Design the NPU's core components, including the PE array, memory hierarchy, and control logic. • Optimize for performance, power efficiency, and scalability. 2. Bit-True Hardware Model Implementation: • Develop a bit-true hardware model of the NPU in C language. • Ensure that the model accurately represents the NPU's behavior, including arithmetic operations, memory access, and control flow. • Validate the model against reference neural network workloads. 3. Cycle-Accurate Modeling: • Create a cycle-accurate model of the NPU to simulate its behavior at the clock cycle level. • Account for pipeline stages, data dependencies, and timing constraints. • Use tools like Verilog, system-Verilog, or specialized simulation environments to achieve cycle-accurate modeling. 4. Performance Analysis and Optimization: • Profile the NPU model to identify bottlenecks and areas for improvement. • Propose and implement optimizations to enhance performance and reduce latency. • Collaborate with software teams to fine-tune the NPU's behavior. 5. Verification and Validation: • Create testbenches and test vectors to validate both the bit-true and cycle-accurate models. • Conduct functional and performance testing to ensure correctness and compliance with specifications. • Debug and resolve any discrepancies between the models and the actual NPU. 6. Documentation and Communication: • Document the NPU architecture, design decisions, and implementation details. • Present findings, progress, and challenges to stakeholders and management. • Collaborate with software engineers, firmware developers, and system architects. Qualifications: • Master's or Ph.D. degree in Electrical Engineering, Computer Science, or a related field. • Minimum of 3 years of experience in NPU architecture design and implementation. • Proficiency in C/C++/Verilog/System-Verilog programming for hardware modeling. • Familiarity with systolic arrays, matrix multiplication, and neural network accelerators. • Knowledge of bit-true modeling, fixed-point arithmetic, and floating-point arithmetic. • Experience with verification tools and simulation environments. • Strong analytical and problem-solving skills. • Excellent communication and teamwork abilities. • Attention to detail and commitment to quality. If you are passionate about NPU architecture, hardware modeling, and want to be part of a team driving innovation, we encourage you to apply. Join us in shaping the future of AI!

⚠️特別說明：此職位需on-site在新竹清大創新育成中心辦公室，無提供遠端工作條件。 ✅主要職責： 1. 高效能記憶體子系統（DDR/LPDDR Subsystem）之整合、開發與驗證。 2. 參與GenAI SoC設計，包括架構規劃、RTL設計、模擬與驗證。 3. 配合後端設計團隊，進行時序分析與設計優化。 5. 進行設計文件撰寫與維護，確保設計過程符合公司開發流程。 6. 針對客戶需求，進行系統分析與客製化設計開發。 ✅基本要求： 1. 電機、電子、資訊工程相關科系畢業，學士以上學歷。 2. 具備5年以上數位IC設計經驗。 3. 熟悉 DDR PHY 架構、控制器、timing calibration與 training 流程 4. 熟悉SoC Bus Fabric設計，具備AXI、AHB等匯流排介面經驗。 5. 熟悉RTL設計 (Verilog / System Verilog)。 6. 了解前端設計流程，包括模擬、合成、時序分析等。 7. 良好的問題分析能力，具備團隊合作精神。 ✅加分條件： 1. 有參與過 LPDDR Subsystem Integration與Silicon Tape-out 並成功量產 2. 熟悉 Synopsys LPDDR、Cadence GDDR IP/Subsystem 3. 熟悉 UPF、低功耗設計流程 4. 熟悉 DFT 、Scan、BIST ✅ Why Join Us 1. 與頂尖技術團隊共事，參與高效能 AI/高速記憶體解決方案開發 2. 自主創新文化，提供技術發揮與產品影響力兼具的工作環境

1. 負責數位電路設計和RTL 和IP design, 模擬和驗證. 2. 與類比設計和系統設計, 佈局設計工程師溝通和協作. 3. 實現FPGA emulation和測試平台開發. 4. 協助量產測試程序的開發. 5. 規格書和Design Document的撰寫. 6. 工作地點在台北內湖

a. Job Description: We are looking for a highly motivated RTL Designer to join our team in developing high-performance digital IPs. The ideal candidate will have experience in Register Transfer Level (RTL) design and verification, with a strong understanding of digital logic, microarchitecture, and ASIC/FPGA development processes. The role involves designing and verifying custom hardware IPs for cutting-edge applications. b. Verification: Develop and execute test plans to verify functionality, performance, and power requirements. Create testbenches using SystemVerilog/UVM for functional verification. Perform simulation, debugging, and root cause analysis for design issues. Conduct code coverage and functional coverage analysis to ensure comprehensive testing. Collaborate with verification and firmware teams to validate IP functionality. c. Qualifications: Bachelor’s/Master’s degree in Electrical Engineering, Computer Engineering, or a related field. 2+ years of experience in RTL design and verification. Proficiency in Verilog, SystemVerilog Strong understanding of digital design concepts, including pipelining, clock domains, and low-power design techniques. Experience with simulation tools (e.g., ModelSim, VCS, Questa) and formal verification techniques. Familiarity with UVM methodology and testbench development. Knowledge of scripting (Python, TCL, Perl, Shell) for automation. Experience with FPGA or ASIC development flows, including synthesis and timing analysis. Strong debugging and problem-solving skills. Excellent communication and teamwork abilities. - Non smoking

我們正在尋找對 FPGA 設計有熱情的初階工程師與資深工程師，負責基於 Xilinx FPGA 平台的邏輯設計與實作。 本職位也需要具備基本的 C/C++ 程式設計能力，進行嵌入式控制、軟硬體整合及模擬驗證。 [工作職責] - 使用 Vivado / Vitis 開發 Xilinx FPGA（Zynq/Artix/Kintex/Virtex 等）之 RTL 模組。 - 撰寫 RTL（Verilog/VHDL）實現高速資料路徑、介面邏輯與控制模組。 - 撰寫 Testbench 進行模擬驗證。 - 利用 C/C++ 開發與 FPGA 互動的測試程式或 ARM 嵌入式軟體。 - 協助進行軟硬體整合、除錯與效能優化。 [必備條件] - 電機、電子、資工、資電等相關科系碩士學位。 - 熟悉 FPGA 設計流程與工具（Vivado、ISE、Quartus 等）。 - 熟悉 Verilog 語言基本語法。 - 具備 C/C++ 程式設計與 Debug 技巧。 - 具備 ARM 嵌入式系統及硬體控制相關開發經驗。 - 具備基礎的數位電路與硬體架構知識。 [加分條件] - 具備 Zynq SoC (ARM + PL) 系統整合經驗。 - 熟悉 AXI Bus、DMA、DDR、SPI、I2C 等介面協定。 - 熟悉高階合成（HLS）。 - 熟悉 Linux 系統及 MCU 系統開發經驗。

我們專注於3D影像立體雙目視覺技術 產品應用於3D 影像辨識、360 度環景拍照、攝影或AR 與VR 職務內容： ★ USB2.0/3.1或 MIPI 介面之2D/ 3D 影像處理與壓縮之 IC 開發 ★ 影像處理與壓縮相關數位 IP暨產品之開發設計、測試、驗證 條件要求： 1. 對IP Verification, System Verification 有興趣 2. 熟Verilog coding 與 ASIC design Flow 與 Timing Closure 3. 或有 SoC IC 開發經驗 4. 對開發人工智慧((AI) 晶片與邊緣運算有興趣者