「【國際大型 IC 設計公司】SoC Design Engineer 晶片設計工程師 (台北/新竹)_207HC」的相似工作

1. USB4/USB3/DP/HDMI/PCIe or high speed serial IO controller development 2. IP integration and going with Design quality check flows (e.g. Lint/CDC/Synthesis/LEC …) 3. Familiar with Xilinx FPGA implementation flow for bit file generation 4. Experience in Xilinx FPGA GTY/GTM Transceivers Controlling is a plus 5. Familiar with Advanced Node Low Power Serial Link and IO/Network Architecture

1.影像應用或訊號處理 IC 研發 2.對數位影像、訊號處理, Verilog/VHDL, 具FPGA design flow 經驗。

- Experience with memory controllers (e.g. DDR DRAM, eMMC and other flash, etc.) - Experience in CPU or various buses (AXI, etc) - Good verilog writing skills - Willingness to work with a variety of tasks

Key Responsibilities • Defect Triage & Analysis: Investigate and categorize reported issues, including incorrect computation results, API failures, and build errors across different distributions. • Build & Compatibility Issue Resolution: Ensure library builds successfully on various platforms and distributions (Ubuntu, Red Hat, SLES, CentOS) and identify root causes of failures. • Client Tool Support: Assist in maintaining and enhancing functionalities within the library tools to support debugging and performance analysis. • Cross-Team Collaboration: Work closely with developers, QA, and support teams to diagnose, prioritize, and resolve issues efficiently.

Responsible for developing custom IP for SoC design from specification definition, circuit design to testing, and familiar with component and process characteristics.

※實際任用職稱依個人相關經歷敘薪。 1.各類平面顯示器驅動晶片數位電路設計 2.參與新產品開發規格定義、區塊規劃、設計模擬、整合和驗證 3.與類比、系統和佈局設計工程師溝通合作，共同研發最具競爭力的產品 4.開發CP 測試程式，從 CP 測試程式流程實際驗證所設計數位電路之可測試性

我們專注於3D影像立體雙目視覺技術 產品應用於3D 影像辨識、360 度環景拍照、攝影或AR 與VR 職務內容： ★ USB2.0/3.1或 MIPI 介面之2D/ 3D 影像處理與壓縮之 IC 開發 ★ 影像處理與壓縮相關數位 IP暨產品之開發設計、測試、驗證 條件要求： 1. 對IP Verification, System Verification 有興趣 2. 熟Verilog coding 與 ASIC design Flow 與 Timing Closure 3. 或有 SoC IC 開發經驗 4. 對開發人工智慧((AI) 晶片與邊緣運算有興趣者

Overview: MOSFET Design Team offers the innovative environment for talents to dive deep into the world of device design, platform development, and research. We offer working locations in both Xindian and Tainan. Come and join us to focus on the most cutting-edge semiconductor materials and applications! Key Responsibilities: • Develop and execute innovative device layouts in line with customer requirements, ensuring optimal functionality and efficiency. • Partner with PE and Quality teams to enhance device reliability and address any arising issues in time. • Establish and continuously optimize SPICE models to reflect the characteristics of both new and existing devices. • Work alongside the PIE team and collaborate with external foundries, paving the way for the next generation of advanced devices. • Drive the research and patenting efforts centered around novel designs, applications, and advanced materials, such as GaN and SiC. • Accomplish additional tasks delegated by the supervisor. Qualifications: • A Master’s degree in EE, Physics, or a related field. • Expertise in power devices, with a spotlight on UMOS, SGT, LDMOS, MLSJ, GaN and SiC. • Comprehensive understanding of device physics and semiconductor manufacturing processes. • Proficiency in semiconductor simulation tools. • Strong English communication skills, catering to both technical and non-technical stakeholders.

請務必投遞官網(12438): https://careers.synopsys.com/job/hsinchu/applications-engineering-staff-engineer-ic-validator/44408/84710683632 You Are: You are an innovative and resourceful engineer with a deep curiosity for solving complex technical challenges at the intersection of hardware and software. With a strong foundation in Electronic Engineering, Computer Science, or a related field, you are adept at leveraging your programming expertise—whether in Python, Tcl, Perl, or similar languages—to streamline and enhance engineering workflows. Your experience within UNIX/Linux environments equips you to navigate high-performance computing scenarios with ease. You thrive in collaborative, cross-functional teams and are energized by the opportunity to work closely with top-tier foundry partners and leading fabless companies. Your keen understanding of physical verification flows—such as DRC, LVS, PERC, FILL, and DFM—sets you apart, and you are eager to deepen your expertise in SoC physical design enablement, process effect analysis, and signoff. You are detail-oriented, capable of producing clear technical documentation, and communicate with clarity and empathy across diverse audiences. What You’ll Be Doing: 1.Delivering advanced physical verification solutions (DRC/LVS/PERC/Fill) for top-tier foundries and key fabless customers, ensuring high-quality silicon signoff. 2.Developing and validating process design kits (PDKs) and verification methodologies in collaboration with R&D and customer teams. 3.Partnering with R&D to innovate and improve Synopsys tools and flows, contributing to the evolution of physical verification technologies. 4.Providing hands-on customer support, troubleshooting issues, and delivering timely resolutions that enhance customer satisfaction and product adoption. 5.Coordinating with internal teams, including product managers and end-users, to align on best practices and ensure seamless integration of new technologies. 6.Documenting technical solutions, validation methods, and customer workflows for knowledge sharing and process improvement. 7.Staying up to date on industry trends and applying new insights to continuously optimize verification processes and tools. The Impact You Will Have: Accelerate the adoption and success of Synopsys physical verification products in leading-edge semiconductor manufacturing processes. Drive the development of robust PDKs and methodologies that enable customers to achieve first-time-right silicon. Enhance the quality and reliability of Synopsys verification tools through direct feedback and collaborative innovation with R&D teams. Strengthen Synopsys’ reputation as a trusted partner to top-tier foundries and fabless customers worldwide. Facilitate faster product cycles and reduced time-to-market for customers by delivering efficient and effective signoff solutions. What You’ll Need: BS or MS degree in Electronic Engineering, Computer Science, or a related field. Proficiency in at least one programming language, such as Python, Tcl, or Perl. Hands-on experience with UNIX/Linux environments and command-line tools. Familiarity with physical verification flows (DRC, LVS, PERC, FILL, DFM) and understanding of complex layout/electrical design rules. Strong investigative, analytical, and problem-solving abilities, with a passion for learning new technologies. Ability to produce clear, concise technical documentation and validation reports. Prior knowledge of tool/runset development/support and experience with SoC physical design is a plus.

負責 Display Port IP 規劃與設計 工作內容:  Display port IP leader  Display port IP architecture definition  RTL design and functional verification  FPGA verification  Synthesis and static timing analysis

a. Job Description: We are looking for a highly motivated RTL Designer to join our team in developing high-performance digital IPs. The ideal candidate will have experience in Register Transfer Level (RTL) design and verification, with a strong understanding of digital logic, microarchitecture, and ASIC/FPGA development processes. The role involves designing and verifying custom hardware IPs for cutting-edge applications. b. Verification: Develop and execute test plans to verify functionality, performance, and power requirements. Create testbenches using SystemVerilog/UVM for functional verification. Perform simulation, debugging, and root cause analysis for design issues. Conduct code coverage and functional coverage analysis to ensure comprehensive testing. Collaborate with verification and firmware teams to validate IP functionality. c. Qualifications: Bachelor’s/Master’s degree in Electrical Engineering, Computer Engineering, or a related field. 2+ years of experience in RTL design and verification. Proficiency in Verilog, SystemVerilog Strong understanding of digital design concepts, including pipelining, clock domains, and low-power design techniques. Experience with simulation tools (e.g., ModelSim, VCS, Questa) and formal verification techniques. Familiarity with UVM methodology and testbench development. Knowledge of scripting (Python, TCL, Perl, Shell) for automation. Experience with FPGA or ASIC development flows, including synthesis and timing analysis. Strong debugging and problem-solving skills. Excellent communication and teamwork abilities. - Non smoking

工作內容： 1. 數位IC電路設計，模擬驗證及下線 2. 數位IC設計流程，包括Linting、Synthesis、DFT、STA...等. 3. FPGA硬體設計 相關應用: 1. 電源管理IC數位電路設計 2. Interface protocol design - I2C、PMBus、SPMI、I3C...etc. 3. Power management state / sequence / fault / charger control...etc. NVM (eFuse/OTP/MTP) controller

1.RTC Module/ IP design. 2.Design synthesis. 3.Design verification. 4.DFT/ siemens tools.

1. 具 0~2年數位晶片設計，或有 0~5年類比晶片設計工作經驗。 2. 具備基本數位和類比電路知識，熟習標準晶片設計流程。 3. 熟習業界常用EDA tools, 或Matlab/ Simulink。 4. 研習過CMOS or BiCMOS 類比設計電路課程，對放大器有基礎認識。 5. Experience in these areas is preferred： * BiCMOS or CMOS high-speed (>20Gb/s) circuit, Linear electrical amplifier & equalizer, High-speed (>25G) CDR/PLL/SerDes. * Linear optical laser driver & receiver (TIA + linear amplifier) 本職位負責類比IC電路的設計、驗證和除錯。這是一個高度技術性的職位，對公司的產品開發至關重要。我們正在尋找一位熱愛類比IC設計並具有相關經驗的人才，以推動公司的技術創新和發展。 如果您對這個職位感興趣，請投遞您的履歷表，我們立即與您聯繫。

This engineer will be responsible for designing and developing digital circuits of liquid crystal on silicon (LCoS) backplanes. You will encompass the entire digital design flow, including specification generation, architecture development, RTL description using System Verilog, verification via developed test benches, logic synthesis, executing place & route tools, and static timing analysis. Key Responsibilities •Lead the design of interfaces for liquid crystal phase modulator pixel arrays, such as column drivers, row drivers, and pixel bias drivers, as well as supporting clock and reset analog circuits. •Define specifications with the module architecture/system engineers. •Review, assess, provide feedback, and develop digital micro-architectures. •Generate RTL to comply with specifications, both manually and through automated generation. •Create a Cadence schematic database of digital blocks using Virtuoso. •Perform System Verilog verification simulations for the design by creating test benches at the block level. •Execute logic synthesis and generate the physical layout. •Create DFT hooks and generate test patterns. •Execute remaining back-end tools, including place & route, static timing analysis, and ATPG. Requirements •BS or MS with 2+ year experience. •Proficiency in System Verilog/Verilog language and simulation. •Proficiency in scripting languages such as Python, TCL, UNIX/LINUX shell, PERL, C/C++. •Experience with synthesis and static timing analysis. •Experience with place & route using Cadence Virtuoso, and verifying database vs schematics. •Knowledge of System Verilog assertions and functional coverage. •Experience with formal verification. •Familiarity with scan testing and participation in design reviews. •Excellent analytical, problem-solving, and debugging skills. •Good communication and teamwork skills, with the ability to work effectively in cross-functional teams. Preferred Qualifications •Knowledge of analog mixed-signal design. •Knowledge of SerDes circuits/IP. •Knowledge of LCOS or LCD IC architecture, column driver, MIPI interface. •Good understanding mixed-signal design and EDA tool configuration/setup. •Knowledge of liquid crystal phase modulators.

先進SRAM 設計及開發

(1) DRAM電路設計與模擬驗證 (2) 具備DRAM ROW/COLUMN/CONTROL/DC/DLL任一或更多電路設計經驗者佳 (3) 具備verilog經驗者尤佳 (4) 了解基本UNIX操作，具備AWK等Programing能力者尤佳 (5) 具備電機電子資訊物理相關背景，無工作經驗可

Job description 1. 5 yr+ hardware schematic and PCB design, planning and verification related work experience. 2. Co-work with IC designers, antenna designers, and product test engineers to design mass production test fixtures such as probe cards, load boards, and module test boards. 3. Co-work with FAE to review customers' application circuits and PCB. 4. Familiar with PCB design software tools (OrCAD, Allegro, Power PCB, CAM350…) . 5. Good knowledge on high-speed digital and analog signal integrity theory. 6. Good knowledge on DC to DC /LDO power integrity design. 7. Good knowledge on SPI, I2C. 8. General PCB debug capability. 9. Good knowledge on PCB fabrication and assembly process. 10. General mechanical concepts. 11. Good soldering ability. KaiKuTek is the world's leading provider of 3D gesture sensors using mmWave Radar with embedded AI accelerator. We possess key technologies in areas such as Antenna-in-Package (AiP), ML algorithm, AI accelerator, as well as 60 GHz radar transceiver design. With a recent merger by JMicron, founded in 2001 and located in Hsinchu Science Park, our product portfolio expands to high-speed SerDes bridge controller SOC's mainly in storage applications utilizing USB, PCIe, and SATA. This new sensing technology will change and redefine human-machine interface as we know today, and mmWave technology combined with high speed SerDes will open door to many new possibilities and application frontiers. KaiKuTek is looking for enthusiastic hardware engineers willing to take upon new challenges of working closely with cross functional teams, including digital IC designers, analog/RFIC designers, firmware engineers, packaging engineers, production and testing as well as marketing and FAE, to optimize the overall SoC performance in terms of power, area, functionality, testability as well as to create proof-of-concept for new customer engagement.

UltraSense Systems, headquartered in Silicon Valley, is revolutionizing human-machine interfaces (HMI) through its cutting-edge SmartSurface technology. Our InPlane Sensing platform seamlessly integrates touch, lighting, and haptic feedback into everyday surfaces, delivering intuitive, responsive, and premium user experiences across automotive, consumer electronics, and other industries. Join our mission to create the next generation of smart, touch-sensitive surfaces that are both functional and aesthetically superior. Summary UltraSense Systems is seeking a creative Senior Engineer, Ultrasound Algorithm Development to help develop the prototype of a groundbreaking new product. In this role, you'll collaborate with a high-caliber team to design and build devices that break new ground in the industry. This role involves hands-on algorithm development, acoustic signal processing, and system development. Key Responsibilities ．Lead design, development, and prototyping of ultrasound sensor systems—from concept through testing and iteration (inspired by Xwave Innovations roles) ．Develop, implement, and optimize acoustic signal processing algorithms, including beamforming (phased array/delayandsum), synthetic aperture techniques, and advanced array processing ．Write clean, efficient, well-documented Python code for simulation, modeling, and real-time signal acquisition/processing ．Build and integrate prototype hardware and firmware components (e.g., piezoelectric transducer interfacing, digitizers, array electronics) ．Conduct simulations, modeling (e.g., FEA or acoustic propagation), and validation testing; iterate to improve system performance ．Analyze sensor data, benchmark performance metrics, debug acoustics chain (from raw signals to processed outputs), and refine algorithms and hardware　accordingly ．Collaborate with cross-functional teams—mechanical, electrical, software—to define system requirements and drive integrative design (common across R&D roles) Minimum Requirements ．Degree: M.S. or Ph.D. in Electrical Engineering, Acoustics, Computer Science, Applied Physics, or a related field ．Hands-on experience (3–5+ years) in acoustic/ultrasound signal processing or sensor systems, including beamforming and array processing (phased arrays, delay-and-sum, synthetic aperture, etc.) ．Strong proficiency in Python for algorithm development, data analysis, and simulation (e.g., with NumPy, SciPy, MATLAB not essential but a plus) ．Practical experience with prototyping hardware—working with transducers, pulser/receiver logic, data acquisition systems, or similar instrument interfacing ．Solid understanding of acoustic wave propagation, ultrasound physics, signal-to-noise enhancement techniques, and array signal processing principles ．Excellent communication, writing, and documentation skills; ability to draft technical reports, collaborate with teams, and present findings clearly (noted across industry postings) Desired Requirements ．Ph.D. in relevant field, with a proven R&D track record, including publications, patents, or conference papers ．Experience with FEA modeling or acoustic simulation tools, especially for transducer design or wave propagation analysis ．Background in device fabrication, CAD design, or microelectronic processing (e.g., GDS patterning) is a plus ．Familiarity with synthetic aperture ultrasound techniques or advanced imaging methods ．Experience developing adaptive or data-driven beamforming (e.g., deep learningenabled approaches for ultrasound) ．Proficiency in embedded platforms or real-time firmware, including porting signal processing algorithms into C/C++ or FPGA/ASIC environments ．Proven ability in small R&D environments—self-motivated, resourceful, and highly collaborative ．Comfortable working in a fast-paced, cross-functional environment ．Creative thinker with a passion for tackling unfamiliar challenges ．Eagerness to contribute to early-stage product innovation and development

【工作內容】 • Work with team members and apply current functional verification techniques to perform and improve pre-silicon verification quality and product Time to Market • Provide the technical leadership to the DV team for the project • Work independently on various DV tasks and provide technical guidance to the DV team. • Be involved technically in the porting/creation of the DV environment for the new design, block and chip level test plan creation and implementation, coverage analysis, and regression cleanup 【職務條件】 • Master’s degree in Electrical Engineering, Computer Science, or related. • Good understanding of ASIC design verification flow. • RTL coding with Verilog/System Verilog and familiar with front-end design flow and C/C++ programming experiences. • Knowledge of Perl, OVL, SVA, SV, UVM, OVM, script programming, etc. 【其他條件】 • MSEE with a minimum of 5 years, or BSEE with a minimum of 8 years of experience in digital ASIC/SOC design verification • MS/BS degree in EE or CS with expertise in digital IP/SOC design verification.