「S－APR Physical Design Engineer｜知名面板驅動IC大廠專案（新竹）」的相似工作

【工作內容】 • 我們正在尋找具備先進製程經驗的 IC Layout 工程師，加入團隊後可以參與高階SoC /Analog IP 的實體實現，並負責以下工作： -Mixed-Mode FinFET Layout 設計與繪製，確保電路佈局在效能、面積與可靠性之間取得最佳平衡。 -進行 FinFET 製程相關的 DRC / LVS / ERC 驗證，確保設計符合法規與 Foundry 要求。 -熟悉 XRC & EM/IR 分析流程，進行可靠性評估，並針對潛在問題提出改善方案。 【職務條件】 • 必備條件：具備 FinFET 製程經驗，能獨立進行版圖設計與驗證。 -具備類比電路佈局經驗，了解電路特性與佈局考量，能與設計工程師密切合作。 -具備良好的溝通能力與團隊合作精神，能在專案時程內交付高品質成果。

【本職缺優先審核至高通官網投遞人選】請至高通官網上傳英文履歷表https://careers.qualcomm.com/careers/job/446705989572 【Talents who apply job through Qualcomm Career Website will be reviewed and considered as top priority】 https://careers.qualcomm.com/careers/job/446705989572 【General Summary】 As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm CPU Engineer, you will lead innovative Central Processing Unit (CPU) design efforts that have a critical impact on industries across the world. Qualcomm Engineers collaborate with cross-functional teams to design, verify, and implement multi-core CPU operations for all Qualcomm Business Units. 【Roles and Responsibilities】 • Collaborate with cross-functional teams (RTL, Physical Design, Circuits, CAD) to address critical physical design challenges in CPU implementations. • Develop innovative techniques within Physical Design and optimization space to meet stringent PPA targets. • Coordinate with CPU Software, Architecture, and RTL teams to understand various CPU use cases and propose impactful PPA optimizations. • Engage with external CAD tool vendors and internal CAD teams to identify and enhance optimization issues related to CPU designs. • Partner with all block-level implementation teams to analyze, implement, and improve optimization methods relevant to the designs. • Partner with Process, SoC and Post-silicon teams to analyze, improve design implementations. 【Must have skill/experience】 • Experience with Synthesis, place and route and signoff timing/power analysis. • Knowledge of high performance and low power implementation techniques • Proficiency in scripting (TCL, Python, Perl) 【Minimum Qualifications】 • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 6+ years of Hardware Engineering, Electrical Engineering, or related work experience. OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 4+ years of Hardware Engineering, Electrical Engineering, or related work experience. OR PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field and 3+ years of Hardware Engineering, Electrical Engineering, or related work experience.

【工作內容】 • Work with team members and apply current functional verification techniques to perform and improve pre-silicon verification quality and product Time to Market • Provide the technical leadership to the DV team for the project • Work independently on various DV tasks and provide technical guidance to the DV team. • Be involved technically in the porting/creation of the DV environment for the new design, block and chip level test plan creation and implementation, coverage analysis, and regression cleanup 【職務條件】 • Master’s degree in Electrical Engineering, Computer Science, or related. • Good understanding of ASIC design verification flow. • RTL coding with Verilog/System Verilog and familiar with front-end design flow and C/C++ programming experiences. • Knowledge of Perl, OVL, SVA, SV, UVM, OVM, script programming, etc. 【其他條件】 • MSEE with a minimum of 5 years, or BSEE with a minimum of 8 years of experience in digital ASIC/SOC design verification • MS/BS degree in EE or CS with expertise in digital IP/SOC design verification.

【職務內容】 ˙需具備HV經驗 Level Shifter（含 HV Device）、Charge Pump、Source Driver、OpAmp / DAC、TCON（含 Digital Layout + Clock Tree） ˙需具備3-5年Driver相關經驗 ˙需熟悉繞線（Routing） ˙Block-Level設計經驗可 ˙能讀懂 Calibre DRC command file 語法佳 ˙具備28/22nm HV製程經驗佳 ˙無需英文能力，全台灣團隊

DESCRIPTION: 1. Responsible for the physical design process of chip numbers from netlist to GDSII 2. Responsible for interaction with the front-end design team to realize the design convergence and optimization of the front and back ends; Comprehensive, static timing analysis 3. Floor planning, power planning and signoff, place and route, timing closure, chip static timing analysis and physical verification 4. IP integration, synthesis, verification and correction 5. Other Assigned Tasks delivered by the Line Manager QUALIFICATIONS: 1. MS degree in EE or related. 2. Familiar with physical design flow, including hierarchical design and low power design is a plus 3. Familiar with EDA tools, such as SoC Encounter/INNOVUS/ICC/ICC2 is a plus 4. Familiar with computer languages such as Perl/TCL/C-shell 5. Self-motivated with good communication skills and team spirit 6. Ability to understand and articulate technical issues. 7. Fluent English is a plus. 8. Experience in 12/5nm design is a plus.

【主要工作內容】 1.Netlist to GDS, including floorplan/powerplan/physical synthesis/clock tree synthesis & routing 2.Chip level physical verification, including DRC/LVS/DFM & tapeout 3.IR-Drop analysis 【需求條件】 1.有使用過ICC/ICC2/laker, 曾做過fully layout & chip level PV 2.工作態度積極認真, 有獨自解決問題能力

ASIC design engineer responsible for post-RTL design flow. He/She will be responsible for block and /or chip level synthesis, timing closure, DFT generation, and ECOs. The responsibilities include but are not limited to. •    Improve the design methodology and flow. •    Synthesis, timing closure, and DFT support for various types of SerDes IPs ranging from 10Gbps to 224Gbps data rates for different applications. •    Collaborate with Analog/Digital design teams to deliver competitive SerDes IP solutions for all the Marvell product lines. •    Provide support to the product teams, for both pre and post-silicon

1. 領導、管理團隊 2. 熟悉 Layout Edit Tool 的操作 3. 熟悉 Physical Verification Tool 的操作 4. 負責 IC 電路佈局、優化和驗證 5. 確保 IC 佈局符合 Circuit Designer 設計需求及產品、製程等規範

(1)Must have BS in CS/EE of relevant experience in IC design field. (2)Familiar with IC design flow, placement and route (P&R), and layout. (3)Circuit knowledge and logic design relevant experience would be a plus.

加入專業 IC 團隊，專責成熟製程的 Analog / Mixed-Signal 晶片開發與版圖設計，實作涵蓋 28nm 節點、ESD 保護與高速 Tx/Rx 模組，適合具備實務經驗並渴望技術突破的版圖工程師。 【工作內容】 • 使用 Laker 或 Virtuoso 進行 Analog / Mixed-Signal 電路之版圖設計 • 使用 Calibre 進行 DRC / LVS 等驗證作業 • 負責 28nm 等低電壓製程節點之 Layout 設計與優化 • 具備 ESD 與 Tx/Rx 電路 Layout 經驗者尤佳 • 與設計團隊密切協作，確保電路性能、面積、可靠度與製程規範之平衡 【職務條件】 • 具備 2 年以上 IC Layout 實務經驗 • 熟悉 EDA 工具：Laker、Virtuoso、Calibre（含 DRC / LVS） • 熟悉 Analog Layout 基礎與高階電路（含 LV、28nm） • 曾參與 IP 整合、版圖組裝與驗證流程 者佳 • 具備主動積極、細心耐心、具抗壓與團隊合作精神，能依時交付任務成果

1.Analog & physical design flow/script development 2.IR/EM sign-off 3.Flip-chip design 4.Physical verification flow

IC layout

1. FrontEnd flow development. 2. Project support and consultant. 3. Develop CAD utility, design automation 4. Work with different process nodes, develop the design flow and methodology

The successful candidate will work with team members and apply his/her design techniques to work on different phases of complex logic design for ASIC/SOC project. The role will include working on the following tasks from time to time: HDL coding, documentation, RTL quality check, cooperate with back-end engineer etc. 【Key Responsibilities】 - Responsible for front-end digital logic design in ASIC/SOC projects. - Perform HDL coding (Verilog/SystemVerilog). - Prepare and maintain design documentation (specifications and design documents). - Conduct RTL quality checks (Lint, CDC, power analysis, etc.). - Collaborate with Backend/Physical Design engineers to achieve timing closure. 【Core Requirements】 - Education/Experience: Master’s degree with ≥ 2 years, or Bachelor’s degree with ≥ 3 years of digital ASIC/SOC design experience. - RTL Design: Proficient in RTL coding using Verilog/SystemVerilog or VHDL. - TO / Front-End Flow: Familiar with front-end design flow, including synthesis, Lint, CDC, and STA. - EDA Tools: Experience with tools such as Lint, CDC check, and PrimeTime PX (power analysis). - Documentation: Ability to write design specifications and technical documents. - Collaboration: Work closely with the Design Verification (DV) team on IP verification. 【Preferred Qualifications】 - Familiarity with CPU architectures (x86/ARM/8051). - Knowledge of AMBA bus protocols (AXI/AHB/APB). - Understanding of PCIe protocol.digital IP/SOC design verification.

1.根據通訊演算法，撰寫RTL code (Verilog, VHDL) 2.數位電路設計。 3.承辦及參與委託給業界或學界之研發案。

1. Work on 3~7nm design implementation, methodology, and sign-off 2. Perform synthesis, DFT, floorplan, clock planning, place and route, timing closure, ECO, IR signoff, and physical verification 3. Manage schedule, resolve design and flow issues, drive methodologies and execution

1.對類比IC Layout 有興趣者, 英文中等以上佳, 歡迎非本科系 2.無工作經驗可 3.相關科系.有英文相關證照者佳 4.流利英文對談優

類比/馬達/電源管理 IC Layout

1. ARM CPU design physical implementation 2. ARM CPU power and timing sign off 3. Physical design flow enhancement for high-speed CPU

1. Analog mixed signal IC layout 2. 熟悉IC Layout tool 3. 熟悉先進製程