「Lead Signal Integrity Engineer」的相似工作

[General Summary] As a forward-thinking technology company, Augentix advances the limits of innovation in "Industrial and Embedded IoT" to deliver next-generation experiences and accelerate digital transformation toward a smarter, more seamlessly connected world. We are seeking a PCB Design Engineer with strong theoretical foundation and simulation driven design methodology to lead high speed board level development. You will be responsible for defining and verifying board level electrical design, ensuring optimal signal integrity across multiple high speed interfaces. You will be supported by experienced layout engineers capable of implementing your design guidance and constraints, allowing you to focus on PCB circuit design and system validation. This position offers the opportunity to build structured PCB design practices, improve team capability, and drive electrical excellence through direct ownership of simulation and cross team collaboration. [Responsibilities] ★ Lead system level PCB electrical design for interfaces such as LPDDR4/5, USB 3.x, SDIO 3.x, MIPI and Ethernet. ★ Define PCB stack up and routing strategy to meet signal integrity objectives. ★ Perform circuit level simulations using tools such as PSpice. ★ Own schematic level electrical planning and define layout constraints for critical signal groups. ★ Provide guidance to supporting layout engineers to ensure adherence to electrical rules and best practices. ★ Correlate simulation results with lab measurements and assist in electrical issue root cause analysis. ★ Document simulation methodology constraint guidelines and validation reports. ★ Occasional business travel across APAC and other regions may be required. [Minimum Qualifications] ★ Familiarity with differential and single ended routing across LPDDR4/5, USB 3.x, SDIO 3.x, MIPI and Ethernet. ★ Proficiency with layout tools such as Allegro. ★ Exposure to EMI mitigation techniques and hands on experience in EMI pre compliance testing. ★ Demonstrated ability to lead layout teams or mentor junior engineers in constraint based PCB design. ★ Ability to create structured documentation and design guidelines to scale internal processes. ★ Strong debugging and problem solving skills with working knowledge of firmware and software to support system level root cause analysis. ★ Comfortable working in a globally distributed, cross-disciplinary engineering team.

BU Overview Consumer, network and datacenter applications change at an exponential pace and the Data & Devices (D&D) business unit at TE Connectivity is at the heart of a continuously expanding connected life. Accordingly, we provide responsive, iterative and fundamentally agile capabilities and conceive, design and manufacture to support today's demands. Our customers are building the devices and the infrastructure that is redefining what information technology means. Our products push markets and meet the ever-changing need of the evolving, more connected, data-driven world. We are enhancing the way we do business, focusing on the most important things and staying agile and responsive to the needs of a faster, more connected world. Job Overview As a Sr. Product Dvl Engineer in the Signal Integrity team you will focus on the electrical design, simulation, and verification-validation testing of high speed products in the connector and/or cable assembly, radio system industry—targeting high speed communications and connectivity within datacenters and wireless infrastructure. You will be expected to independently work on projects in the areas of signal integrity for product and system design including modeling, simulation, testing and circuit board layout. You will work collaboratively within a broader cross functional team of mechanical, manufacturing, & operations to execute leading edge products designs. You will be the subject matter expert for the signal integrity performance of a product/platform beginning with the initial analysis through prototype fabrication & evaluation, and production verification testing. You will tackle challenging design problems and utilize simulation tools to guide complex designs toward success. Responsibilities: •Subject matter expert in signal integrity design, simulation and validation activities through product development cycles •Establishing signal integrity design performance/functional requirements for new products •Performing signal integrity simulations for multiple high-speed standards on each product. This includes determining the correct simulation methodology and setup to use, as well as a good understanding of the criteria for each interface. •Performing PCB design schematic and layout reviews •Creating actionable recommendations based upon design reviews and simulation results •Guiding connector design and component qualifications from a signal integrity standpoint. Making data driven decisions about the product functionality and areas for improvement. Required Skills/Experience: •Bachelor’s degree in Electrical Engineering, Master’s degree preferred •Minimum of 5 years of work experience in a signal integrity engineering role •Experience with interconnect design or experience with connector &/or cable/cable assembly design (high speed twinax cables, direct attach copper (DAC) cables), &/or RF antenna, RF sub-system •Signal integrity analysis tools (Agilent ADS, Ansys HFSS) •A solid understanding of electromagnetic theory and electrical circuit behavior •Strong analytical capabilities to interpret simulation and lab data to identify issues and provide solutions to fix identified problem. SixSigma methodologies or other strong data analytics background a PLUS. •Familiarity with printed circuit board design, fabrication and assembly. Proficient in Altium a PLUS •Experience in project leadership, especially as it applies across design, development & manufacturing teams •Excellent verbal and written communication skills •Ability to work in a global environment – able to accommodate varying time zones, fluent in English (verbal/written), able to collaborate with individuals across geographies •Individual must be highly motivated, a quick learner, and able to work independently

PRIMARY PURPOSE: As a SI Engineer, you are responsible for verification and characterization in connector design. You will work closely with the mechanical engineer to ensure new design rules, manufacturing processes and material that can fit our goals. DUTIES AND RESPONSIBILITIES: 1.Provide technical support to sales team for CCDC high speed products and helpcustomer to solve interconnect challenges. 2. Perform SI simulation and solve the challenge of SI terms to meet customers. 3.Be responsible for high-speed connector design, simulation and validation through product development cycles for CCDC. 4.Perform pcb design and layout reviews. Conduct measurement and perform the good correlation or find the approach to minimize the gap. 5. Research the next generation platform and committee’s latest specification. 6.Help devise strategies to differentiate our products and solutions from our competitors. 工作簡介: 作為SI工程師，您將負責連接器設計的驗證和特性分析。您將與機械工程師緊密合作，確保新的設計規則、製造流程和材料符合我們的目標。 工作內容: 1. 為CCDC高速產品銷售團隊提供技術支持，並協助客戶解決互連挑戰。 2. 進行SI仿真，並解決SI術語的挑戰，以滿足客戶需求。 3. 負責CCDC產品開發週期內的高速連接器設計、模擬與驗證。 4. 進行PCB設計和佈局評審。進行測量並進行良好的相關性分析，尋找最小化差異的方法。 5. 研究下一代平台和委員會的最新規範。 6. 協助制定策略，使我們的產品和解決方案與競爭對手脫穎而出。

1. Signal integrity analysis, optimization, and channel risk assessment 2. Simulation flow development and improvement 3. Develop PCB SI/PI simulation methodology and analysis flow 4. Provide system level SI/PI design guideline or reference design 4. Channel simulation for high speed digital data bus 5. Skill in Ansys, Sigrity, Keysight simulation tools

工作內容 1. 負責Ansys SIwave/HFSS/Q3D 等高頻軟體技術支援，包含售前/售後支援、教育訓練 2. 拜訪客戶介紹、推廣軟體以及解決方案 3. 與原廠技術團隊對接，協助溝通/解決客戶問題、學習軟體新功能 4. 高頻相關工程專案規劃與執行 5. 支援公司市場行銷活動 ---------------------------------------------------- 本公司具備Ansys產品專業技術人員，擁有廣大的技術資源供學習， 市場遍及台灣、中國及東協等地。 我們不斷地開拓新技術及市場，誠摯希望有志一同的你加入~ 歡迎光學、電磁學、電子電路、電磁干擾、光波導、矽光子各領域專家加入我們的團隊!! 思渤科技培養的不只只針對工作需求的專業工程技術人才， 更是培養技術人才自身技術品牌的職涯延伸， 讓你不單只是單一技術在此發展， 而是廣闊長遠的打造出個人技術品牌知名度， 讓你在專業領域中與更多佼佼者一起發光發亮!! ｜遠距辦公。節省通勤成本。溝通不斷線｜ ☆業務試用期三個月通過後，即可申請遠距辦公方式！ ☆每週只需進公司辦公一天，剩下四天靈活運用外勤出差或在家辦公，節省塞車通勤時間，線上溝通快速不斷線。 ｜舒適好開公務車。公務拜訪便利又安全｜ ☆提供三年內新車預約公務拜訪使用，安全又舒適。 ☆不需自己養車，找車位，公司定期保養管理，外勤無負擔。 ｜薪獎優渥。輕鬆get百萬年薪！｜ ☆業績獎金 ☆盈餘獎金 ☆年終獎金 ☆中秋、端午獎金 ☆配發公務機 ☆結婚禮金/生育津貼 ☆推薦人才獎金 ☆近3年平均調薪幅度3~5%

1. 鍋爐設備操作、保養及故障排除。 2. 日常業務執行及相關作業資料的電腦輸入。 3. 其他主管交辦事項處理。 4. 具鍋爐證照者佳，未具證照公司將安排與補助考照。

Job Description: 1.Managing/Lead a technical team working on various aspects of SI and PI for high speed interfaces, including modeling (board level signal and power delivery network, as necessary for the project), time and frequency domain analysis for SI and PI electrical performance evaluation of Server & Storage industry and correlation to measurement for the various products. 2.Ensuring that processes for various methodologies are executed effectively and accurately. Develop automation tool to optimize SI flow in advance. 3.Collaborating with cross function team for development and continued optimization of methodologies for modeling and analysis as needed. 4.Occasionally Supporting PM & Technical Lead with stack up design & high-speed risk assessment for service to external customer as needed for RFQ proposal. 5.Occasionally Supporting path-finding activities through simulation for electrical issue analysis. Qualifications: Successful candidates for this position will have: •Bachelors or Masters in Electrical/Electronics Engineering w/10 years of industry experience •Desirable previous experience being people leader •Required courses covering electromagnetic, transmission line or similar fields of study or experience. •Strong SI/PI/EMI theory and application, modeling, analysis, simulation •Able to communicate with PCB manufacturer & PCB material vendor to enhance Stack up design. •Experience with, and intermediate working knowledge of E.M. field solvers), time and frequency domain simulation tools like Polar, SIWAVE, HFSS, HSPICE, ADS, PowerDC etc.. •Deep understanding of electromagnetic and transmission line theory, general I/O design, signal integrity, differential and single-ended interface technologies. •Deep understanding of high-speed interface loss budgets and jitter analysis •Expertise in Printed Circuit Board (PCB) layout design techniques & constraint Setting by using Cadence Allegro. •Experience in design and analysis of high-speed single-ende Personality: •Pro-active – Candidate will be expected to identify gaps and opportunities and address them with minimal supervision. •Collaborator – Candidate will be expected to work with various teams globally; and support both internal as well as external customers. •Communicator – Candidate should be able to clearly convey necessary details of complex issues and corresponding solutions in both written and verbal formats. The information we collect: We may collect personal information that you choose to submit to us through the Website or otherwise provide to us. This may include your contact details; information provided in online questionnaires, feedback forms, or applications for employment; and information you provide such as CV/Resume. We will use your information for legitimate business purposes such as responding to comments or queries or answering questions; progressing applications for employment; allowing you to choose to share web content with others or; where you represent one of our customers or suppliers, administering the business relationship with that customer or supplier.

【產品範疇】 1.DDI / TP / TDDI/ TCON/ Power等顯示相關產品 【工作內容】 1. SI/PI/EM issue solving, performance optimization, and design rule development 2. Chip/PKG/Board simulation and measurement for SI/PI/EM issue. 3. Co-work with system engineers, IC designers, and customers on product design-in tasks.

1. 訊號完整性分析與設計建議 2. PCB佈局之規範與檢察 3. PCB疊構評估與設計 4. 高頻量測/驗證 5. 完成上級主管交辦事項

a. SI訊號/PI電源完整性模擬分析 (Pre-Layout & Post-Layout) b. PCB/Layout設計建議與Guideline制定 c. SI/PI/EMI新技術專研與導入

Main Responsibilities: • Perform signal integrity analysis (frequency/time domain) for 224G PAM4 and above. • Conduct PI DC/AC analysis, power plane design, and optimization. • Analyze high-speed serial channels and DDRx SI, including ASIC breakouts, connectors, and cables. • Collaborate with ASIC vendors for link training and system-level integration. • Communicate effectively with Tier 1 hyperscale data center customers. Secondary Responsibilities: • Use tools like HFSS, SIwave, ADS, PowerDC, OptimizePI, and Hyperlynx for analysis and optimization. • Familiarity with COM configuration spreadsheets. • Experience with switch/server products is a plus.

1.＂Chip+PKG+Board＂ modeling & co-simulation for pre-silicon SI/PI/EMC analysis. 2.Co-work with RD/CAD/SE for chip design-in SI/PI/EMC issue support. 3.Gbps interface SI/PI co-design and validation, such as DDR1~4, LPDDR1~4, HDMI, VBO, eDP, MIPI, etc. 4.Provide pkg/board-level SI/PI/EMC design guideline or reference design. 5. Familiar with transmission line theory. 工作地點:台北

1. Electromagnetic simulation and electrical modeling by using Ansys EM suite. 2. SI/PI high frequency / high speed signal integrity / power integrity / antenna radiation with Ansys EM/ADS systems. 3. 3D full wave FEM/FDTD large-scale simulation and validation with EMpro and HFSS HPC. 4. Signal emulation and performance simulation in PCB/Substrat of optical module.

• Implement tasks according to all management systems • Maintain the process SOP documents • Trouble-shooting & process improvement to increase the production yield • Conduct the evaluation of new product transfer • Conduct the evaluation of new raw materials • Lead the samples ENG trial • Support Continuous Improvement activities

1. Ensure PKG design is optimized with SI/PI/Thermal requirements. 2. Create the PKG/RDL/Subtract SI 3D modeling and perform extraction of S-Parameters and RLGC model. 3. Full-wave modeling of VIAs, Connectors, Package and PCB channels, components using 3D full-wave EM tools. 4. Provide the CM(Construction rules) and Design Rules(guidelines) for the PKG/RDL/Subtract design. 5. Provide the Substrate manufacturing process and material property. 6. SI(Signal integrity) simulation and optimization on package stack-up, power/ ground plane assignment and optimization, decoupling cap locations to minimize power ground noise. 7. PI(Power integrity) analysis for state of art package/system designs, which include but not limited to package layout model extraction, transient noise analysis to meet the silicon noise spec, decoupling strategy and analysis. 8. CTK(Crosstalk) analysis and reduction on-package considering mutual-effect by on-die, on-silicon interposer and on-PCB. 9. SSN(Simultaneous Switching Noise)/SSO analysis for I/O (DDR5/4/3, LPDDR5/4/3, etc.) power domain. 10. Eye diagram(ZRZ/PAM4) and jitter analysis for CPS(Die Chip-PKG-System PCB) co-simulations. 11. Familiar with trade-offs among package cost, technologies, design, performance, power, and thermal requirements. 12. Familiar with assembly and substrate manufacturing process is a plus. 13. Familiar with programming/scripting in Java, VBScript, PERL, TCL, MatLab and/or equivalent. 14. Experienced in SI PI automation tool development with Python or PyAEDT is a plus. 15. Working with ASIC/HW/Production team.

歡迎2026年畢業並正在找尋研發替代役的同學申請! What You'll Be Doing: • Post-layout model extraction for project review sign-off • pre-layout model extraction for DOE • Work closely w/ Package and PCB Design teams to design and ensure link performance meets expectation before tapeout • Develop novel algorithms & new methodologies to improve SI/PI/EMI modeling efforts • Work w/ Application Engineering teams to support customers w/ SI/PI questions • Support signal integrity simulation and analysis for interfaces PCIE, NVLink, display, LPDDR etc. What We Need To See: • MS in EE and majoring in SI/PI technology or equivalent experience, • Strong understanding of electromagnetics, specifically electromagnetic waves including transmission line theory and via properties, and the SI/PI/EMI applications; S/Y/Z parameters; discrete signal processing knowledge • Know how to use ANSYS HFSS/Q3D/SIwave/Designer, Synopsis HSPICE, Cadence PowerSI, and Keysight ADS • Understanding of high-volume manufacturing variations and impact to channel signal integrity is a plus • Familiarity with high-speed I/O design concepts including clock generation, transmitter & receiver design, and equalization schemes • Familiarity with transient simulation in tools and understanding of eye diagram methodology • Exposure to lab measurements including VNA & TDR, and oscilloscope experience • Passionate about SI/PI work Ways To Stand Out From The Crowd: • SI analysis flow including frequency and time domain simulation • PDN analysis flow including model generation and time domain simulation • PSIJ Analyses involving co-simulation of circuits and PDN models • Experience w/ Matlab, Python, VBS, and C • RF/microwave engineering; EMI/RFI analysis capability 應徵方式: 請提供以下資料： • 英文個人履歷 • 學士+碩士成績單 (中英文皆可) 提交申請: 請將上述資料投遞至104，符合資格者將會收到進一步的聯繫通知。

1. Performing DC IR drop and AC impedance simulation. 2. Improve simulation/validation efficiency and performance by automation. 3. Execute SI/PI/RF/EMI verification for the system requirements. 4. Build up SI/PI simulation and measurement correlation database. 5. Build up design and test capability including design guidance and lab setup. 6. Working with HW teams to optimize high-speed signal.

職務內容： • 進行SI/PI模擬與分析工作，包括訊號完整度、電源完整度、阻抗分析、CCT和Crosstalk分析。 • 提供SI/PI問題診斷、技術支持及解決方案，確保跨部門協作的順暢進行 • 進行Multi-Task模擬進度的規劃、追蹤與協調，確保專案如期完成並滿足技術要求 • 與客戶、廠商進行技術討論、問題應答和解決方案解釋 • 實現SI/PI設計自動化 具備能力： • 對 SI/PI 模擬技術有強烈的學習興趣，並對硬體設計充滿熱忱。 • 熟悉或有興趣學習 HFSS、ADS、Spice 或其他模擬工具的操作和應用。

Purpose of this Position 深入研究高速訊號，在高速硬體電路Signal Integrity上提供最佳設計且確保生產品質 Major Areas of Responsibility 專案研發 - Perform high speed signal integrity simulation including 10G/40G、25G/100G、PCIE、SATA、DP、USB、DDR3/DDR4/DDR5. - Perform pre-layout, layout constraint, and post-layout simulation processes. - PCB stackup design and layout review for high speed signal and PDN. - Build component models to ensure the correlation between SI/PI simulation and measurement. - Solid SI experience in resolving technical issues and performing detailed analysis. 團隊合作 - Collaborating with EE teams to refine high-speed signal performance. - Collaborate with the layout engineer to provide clear layout guidelines and enhance footprint optimization.

該職務隸屬於LOTES嘉澤端子研發中心，為長期外派RD職缺! Job responsibilities: 1. 與產品設計人員溝通討論各項高頻參數規格。 2. 針對產品高頻與機構需求提出設計建議。 3. 設計並驗收產品之高頻測試治具。 4. 進行高頻高速信號測量與模擬。 5. 與其他研發團隊協作，提供高頻領域的技術支援和解決方案。