「台灣半導體研究中心-(114-064)元件製程工程或研究人員_蝕刻薄膜組」的相似工作

1.專利申請管理: (1)協助準備專利申請文件 (2)與專利代理機構合作，追蹤專利申請進度或回覆文件 2.專利維護與資料管理: (1)負責專利維護並管理專利年費繳納 (2)建立與更新專利資料庫，維護專利清單與檔案 (3)定期製作專利狀態報告，提供管理層決策參考 3.內部協調與跨部門溝通，確保專利策略執行一致性 4.技術審查會議召開與執行 5.技術轉移與推廣所需行政作業，包含項目洽談、合約簽訂、收款及系統登錄等一應行政流程處理 6.支援主管交辦的其他專案或任務

1. 專案整合服務之諮詢、接案討論及分析執行 2. 相關工程問題回覆與專案報告撰寫 3. 案件排程與實驗資料判讀 4. 交期回報/實驗資料傳送 5. 回報案件daily status與主管交辦事項 6. 與國外客戶討論相關分析案件 7. 小夜班津貼優於業界 8. 年薪依個人表現而異，表現優異之資深工程師年薪可達100萬，表現優異之工程師年薪可達85萬

1. MOSFET device research and development, especially Trench MOSFET/ SGT/ SJ. a). Define device layout design and product design rule b). TCAD simulations to build device structure c). Device measurement d). DOE plan for MOSFET new product 2. Interface with Product engineer and Marketing. 3. EFA/ PFA for trouble shooting 4. Build related patent for new design

1. 設計與模擬光電元件 2. 撰寫設計規格與圖面 3. 協助製程團隊完成投片 4. 分析量測數據與驗證結果 5. 撰寫報告文件支援驗證作業 6. 參與跨部門與客戶溝通

1. To improve device yield &CIP in order to meet customer request and customer service. 2. Identify and solve process and device problems. 3. Support for customer visit and audit.

1.負責操作SIMS、XPS、XRD、OM等相關儀器檢測樣品表層狀況，以避免後續異常狀況發生 2.制定數據採集策略，透過元素資料庫及分析經驗，彙整相關資訊，並推薦校正措施給客戶 3.做二休二，每3-6個月輪調乙次，訓練期(3個月-6個月)滿後開始配合輪班 4.每月依績效表現額外發放點數獎金 5.表現優秀，培養二年後年薪可破百萬

工作內容： 1.晶片電路驗證分析 2.客戶案件問題討論 3.年薪依個人表現而異，表現優異之工程師年薪可達85萬，表現優異之副工程師年薪可達75萬 4.夜班津貼優於業界

1.黃光製程開發 2.塗佈製程開發 3.產品失效分析與改善 4.初期需在林口廠受訓，待受訓完成於新竹上班

【必備專業技能】 1. 熟悉以下一至多項技術方向： • 巨量轉移方法：Laser Lift-Off、Stamp Transfer、Electrostatic Transfer、Fluidic Assembly等 • 轉移設備開發與優化：熟悉 pick-up/release 原理與自製設備設計 • 熟悉LED 結構，製程，特性 • 熟悉製程良率管理與失效分析（如破片、黏附力不足、位置偏移） 【實驗與分析能力】 • 能設計 DOE、建立良率模型、進行參數優化 • 熟練使用： 光學顯微鏡 / AOI / 3D Profiler/ Python / JMP / Excel VBA 等分析工具 【軟性能力與合作面】 • 具備高度動手能力與 troubleshooting 能力 • 跨單位（設備/製程/設計/品管）協作與專案追蹤能力 • 能撰寫中英文技術報告與簡報，參與客戶端或內部技術提案 • 對巨量轉移新技術、新材料具研究熱忱與技術前瞻思維

1. 產品良率改善及製程流程優化 2. 新製程開發及導入量產 3. 異常產品分析與處理 4. 半導體元件光電流電壓特性量測及分析

1.執行原物料及廢棄物採樣分析化驗 2.採樣分析數據統計紀錄 3.管理化驗室設備、藥品及檢驗文件 4.協助製程問題之排除 5.系統文件化管理

Your Job As an Advanced Wafer Level Package (WLP) Engineer, you will lead the development of cutting-edge wafer-level packaging technologies. Your role encompasses pioneering heterogeneous integration, 2.5D/3D packaging, chiplet integration, and high-density interconnect solutions. You will develop and validate advanced packaging processes such as RDL, TSV, Hybrid Bonding, Micro-bump, and Fan-Out. Additionally, you will perform material characterization, analyze packaging structures, resolve reliability issues, and collaborate closely across functions to ensure successful technology implementation and prototype development. Our Team You will be part of the DSS Division, within the R&D Component Engineering department, working closely with the Advanced WLP Senior Manager and cross-functional teams including design, integration, testing, reliability, as well as external partners such as material, equipment, and substrate suppliers. Our team is dedicated to pushing the boundaries of semiconductor packaging technology through innovation and collaboration. What You Will Do - Develop and validate advanced wafer-level packaging processes including RDL, TSV, Hybrid Bonding, Micro-bump, and Fan-Out. - Execute the development of heterogenous integration, 2.5D/3D packaging, chiplet integration, and high-density interconnect (HDI) solutions. - Conduct comprehensive material characterization and analyze packaging structures to identify opportunities for process optimization. - Define process parameters and establish design specifications to ensure manufacturability and high yield. - Support the introduction of new technologies and prototype sample development. - Perform failure analysis (FA) and address reliability issues to enhance product performance. - Collaborate cross-functionally with design, integration, testing, and reliability teams to ensure seamless project execution. - Liaise with material, equipment, and substrate suppliers to evaluate the feasibility and integration of new technologies. Who You Are (Basic Qualifications) - Master's degree or higher in Electrical Engineering, Materials Science, Mechanical Engineering, Physics, Chemical Engineering, Optoelectronics, or related fields. - Minimum of 2 years' experience in semiconductor packaging or process development. - Proficient in at least one of the following areas: RDL/Fan-Out process technology, TSV/Micro-bump/Hybrid bonding, Si interposer/CoWoS/InFO/3D IC, or material and structural reliability (thermal, mechanical, electrical). - Strong problem-solving skills and ability to collaborate effectively across functions. - Proficiency in reading and understanding English technical documents. What Will Put You Ahead (Preferred Qualifications) - Experience in wafer-level or advanced packaging technologies. - Hands-on experience in failure analysis (FA) and reliability testing. - Practical experience with wafer fabrication or back-end process operations. - Up-to-date knowledge of industry trends in advanced packaging technologies.

1. 半導體使用之溶液純化技術開發、測試、評估、製程改善及放大 2. 專利、期刊新技術搜索及分析 3. 實驗數據整理、分析與報告 4. 跨部門溝通 5. 品質問題分析 6. 產品技術導入文件編寫 7. 關鍵技術保密 8. 協助研發專案時程管控、成本評估及改善

1. 線上產品異常處置與調查 2. 工程品製作 3. 生產線教育訓練 4. 專案改善執行 【薪資說明】 ◎依學經歷、科系、經驗相關性、特殊需求證照及專長等條件核敘個人薪資

1. 材料, 高分子材料, 化學, 化工相關背景 2. 開發產品材料試驗 3. 材料評估測試與數據收集分析 4. 黃光實驗室設備操作及材料分析儀器操作 5. 對研發有熱忱、具責任心 6. 完成主管交辦研發事項 7. 須配合排班(含中班, 晚班以及假日班)

1. 生產設備的參數調整與設定 2. 操作流程 SOP 撰寫 3. 線上人員的教育訓練 4. 生產異常狀況的排除 5. 製程開發或優化及改善 6. 主管交辦事項

1. 產品開發及黃光測試 2. 材料相容性測試與資料庫建立 3. 競爭品分析 4. 相關數據收集、整理 5. 主管交辦事項

1. 負責新材料的評估、測試、分析與選擇。 2. 開發新型材料、元件及其製造技術。 3. 負責新產品或技術的製程開發及導入。 4. 制訂新產品、新工藝開發計劃所需儀器設備要求和計劃。 5. 制訂新產品檢驗標準。 6. 專利申請，與搜查佈局。 材料研發人員在公司中扮演重要的角色，負責新材料的評估、測試、分析與選擇，開發新型材料、元件及其製造技術，進行新產品或技術的製程開發導入等工作。這個職位的發展前景非常好，隨著公司業務擴展，未來還有更多的成長空間。 如果您對這個職位感興趣，請盡快提交您的履歷表和求職信，我們期待與您見面！

You will be responsible for manage and control shopfloor related to ensure quality / delivery / cost and safety meet company standard setting and meet government requirement. Coordinating related department to let production running smoothly. You will also join operation module team activity to ensure projects continue progress. 管理並掌握生產線相關事宜並確認可滿足品質/交期/成本及安全之相關需求可合乎公司標準規範或政府相關法規規定。協調支援單位提供必要支援以利產線運行。並加入營運處相關專案，以利專案推展順利。 What you will be doing: • To lead production line meet quality / delivery and cost standard 帶領生產線產出合乎品質交期成本的產品。 • To lead production line meet company policy and government requirement 帶領生產線符合公司政策及政府法規需求 • To coordinate related department let production line running smoothly. 協調其他相關部門提供必要支援以利產線順利生產。 • To support operation teams’ activity to ensure projects continue progress. 支援營運團隊相關活動並確認相關專案可順利推展。

Job desicription: Our Design Team specializes in the challenging field of Non-Volatile Memory (NVM) IC circuit design. We are actively seeking an experienced Analog Circuit Design Engineer to contribute to our cutting-edge developments in embedded NVM solutions and surrounding circuitry. As a key member of our team, you will be responsible for the design, verification, and debugging of essential analog building blocks like Bandgap references, LDOs, and Charge Pumps. A significant part of your role will involve designing critical memory peripheral circuits for NVM IP and test chips, including Array interfaces, Decoding logic, and Sense Amplifiers. Your responsibilities will span the design lifecycle, from contributing to IP specifications and core circuit design to ensuring performance through layout optimization and comprehensive corner simulations of NVM IPs. We are looking for candidates with proven expertise in analog circuit design, ideally with prior experience in embedded memory or NVM technologies. If you are an experienced analog designer eager to tackle complex challenges in non-volatile memory, we encourage you to apply and help shape the future of memory technology.