THE ROLE
The Lead Signal Integrity Engineer is a technical leader responsible for advancing Isola’s laminate materials to meet and exceed high-speed electrical and signal integrity (SI) performance requirements. This role provides mentorship and direction to the Signal Integrity team in Taiwan, drives innovation in SI test methodologies, and ensures strong technical engagement with global OEMs. The Lead serves as a recognized authority in SI, bridging customer needs with material performance and representing Isola in the high-performance electronics community.
KEY RESPONSIBILITIES:
Customer-Facing Technical Support:
• Lead technical engagement with OEMs and direct customers on high-speed laminate characterization.
• Act as primary technical contact for SI-related design validation and adoption cycles.
• Oversee the creation of technical reports, white papers, and collateral for internal and external use.
Strategic & Technical Leadership:
• Define and develop advanced SI measurement, modeling, and simulation methodologies.
• Collaborate with Product Management, R&D, and Sales to ensure alignment of SI capabilities with product strategy.
• Represent Isola as a thought leader through publications, conferences, and industry forums.
Organizational Management:
• Mentor, guide, and grow the Taiwan-based Signal Integrity Engineering team.
• Establish scalable, cost-effective SI test methods that accelerate R&D and customer response.
• Drive alignment with global Application Engineering teams to ensure best-in-class technical service.
Technology & Standards Thought Leadership:
• Maintain expertise in SI methods, PCB processing effects, and high-speed digital design requirements.
• Contribute to industry standards development and support customer forums on SI requirements.
QUALIFICATIONS & EXPERIENCE
• 8+ years of experience in signal integrity engineering, PCB laminates, or high-speed design.
• Expertise in VNA measurements, probing techniques, and advanced SI methodologies.
• Experience with PCB manufacturing and processing effects on SI performance.
• Demonstrated leadership and mentoring experience.
• Proven record of technical publications, white papers, or conference presentations.
EDUCATION
• PhD or Master’s in Electrical Engineering or related field required.
OTHER CONSIDERATIONS
• Fluent in English – required for global communication and technical documentation.
• Proficiency in Mandarin Chinese – strongly preferred for engagement with Taiwan/China teams and customers.
• Ability to travel regionally and globally as needed.
Purpose of this Position
深入研究高速訊號,在高速硬體電路Signal Integrity上提供最佳設計且確保生產品質
Major Areas of Responsibility
專案研發
- Perform high speed signal integrity simulation including 10G/40G、25G/100G、PCIE、SATA、DP、USB、DDR3/DDR4/DDR5.
- Perform pre-layout, layout constraint, and post-layout simulation processes.
- PCB stackup design and layout review for high speed signal and PDN.
- Build component models to ensure the correlation between SI/PI simulation and measurement.
- Solid SI experience in resolving technical issues and performing detailed analysis.
團隊合作
- Collaborating with EE teams to refine high-speed signal performance.
- Collaborate with the layout engineer to provide clear layout guidelines and enhance footprint optimization.
PRIMARY JOB DESCRIPTION:
• Responsible for performing signal integrity and power integrity simulation analyzing DIMM products in different form factors.
• Work with layout team and NPI team for achieving good board routing and releasing to production
• Will interface with SMART global design teams
PRINCIPAL DUTIES AND RESPONSIBILITIES:
• Perform channel margin analysis to provide design tradeoffs among package, board, and connector on products starting from the technical specifications from different controller and NAND flash vendors in different form factors
• Perform PCB timing analysis, work with layout designers and hardware engineers to implement all signal integrity rules
• Perform PCB power margin analysis, work with layout designers and hardware engineers to implement all power integrity rules
• Develop layout signal/power integrity rules guideline or document on new products starting from the technical specifications from different DRAM vendors in different form factors
• Capability to execute trouble shooting and provide workable solution to SMART global R&D teams and customers
• Communicate and work closely with global R&D teams to achieve targeted schedule for PCB board release
• Write a Layout guidance document. Organize and research technical reports and share
1.PCB stack-up design & Constraint Rule setting.
2.Provide SI/PI design suggestions for PCB layout.
3.Signal integrity analysis of high-speed and low-speed signal interfaces.
4.Power integrity design includes DC impedance, AC resonance and capacitance optimization.
5.In addition to Cadence 2.5D EM solution as a daily necessary software, AMD SeaSim/S2Eye, Intel ICAT/IMLC/CCT are also required.
6.Use TCL and Python to shorten the complicated software operation process, generate reports and perform DOE analysis.
7.Familiar with PCB test coupon TDR/TDT measurement and Delta L 4.0 Measurement.
1. 針對高速介面進行信號完整性模擬。
SI simulation : TDR, S parameter,Eye diagram,Crosstalk..
2. 電路板電源完整性模擬。
PI simulation : IR Drop , PDN..
3. 對於佈局圖給予改良建議。
Polar應用及評估PCB & VNA材料選擇方式
4. 信號完整性異常除錯。