「【知名IC 設計公司】AI ASIC_SoC Design Engineer 晶片設計工程師 (台北/新竹)_207SS」的相似工作

The successful candidate will work with team members and apply his/her design techniques to work on different phases of complex logic design for ASIC/SOC project. The role will include working on the following tasks from time to time: HDL coding, documentation, RTL quality check, cooperate with back-end engineer etc. 【Key Responsibilities】 - Responsible for front-end digital logic design in ASIC/SOC projects. - Perform HDL coding (Verilog/SystemVerilog). - Prepare and maintain design documentation (specifications and design documents). - Conduct RTL quality checks (Lint, CDC, power analysis, etc.). - Collaborate with Backend/Physical Design engineers to achieve timing closure. 【Core Requirements】 - Education/Experience: Master’s degree with ≥ 2 years, or Bachelor’s degree with ≥ 3 years of digital ASIC/SOC design experience. - RTL Design: Proficient in RTL coding using Verilog/SystemVerilog or VHDL. - TO / Front-End Flow: Familiar with front-end design flow, including synthesis, Lint, CDC, and STA. - EDA Tools: Experience with tools such as Lint, CDC check, and PrimeTime PX (power analysis). - Documentation: Ability to write design specifications and technical documents. - Collaboration: Work closely with the Design Verification (DV) team on IP verification. 【Preferred Qualifications】 - Familiarity with CPU architectures (x86/ARM/8051). - Knowledge of AMBA bus protocols (AXI/AHB/APB). - Understanding of PCIe protocol.digital IP/SOC design verification.

我們專注於打造次世代電路模擬專用硬體加速器，誠徵數位IC設計師，加入我們的行列，透過數位電路設計與驗證實力，推動電路模擬的極致效能與可靠性。 你將負責： ▪️ 設計電力分析專用晶片架構及系統 ▪️ RTL設計與功能驗證，確保系統正確性與效能表現 ▪️ 參與SoC數位區塊的功能設計、整合與驗證 ▪️ 進行綜合、時序分析與低功耗設計優化 我們期待你具備： ▪️ 電子/電機工程學士以上學歷 ▪️ 精通Verilog/SystemVerilog與RTL設計流程 ▪️ 熟悉綜合與時序分析方法 ▪️ 具備DSP演算法硬體實現經驗 ▪️ 理解低功耗設計技術與實務 專業工具： ▪️ Synopsys Design Compiler ▪️ Cadence Genus ▪️ Mentor Graphics 加分條件： ▪️ 具備完整SoC設計專案經驗 ▪️ 熟悉UVM或其他驗證方法學 ▪️ 有28nm以下先進製程設計或量產經驗 ▪️ 具備電力電子或電源管理電路相關背景 如果你熱愛透過數位IC設計挑戰能源晶片的極限，歡迎加入我們，打造更智慧的硬體未來！

我們專注於打造次世代電路模擬專用硬體加速器，誠徵SoC系統架構工程師，加入我們的行列，透過系統整合驅動硬體創新，徹底改寫電路模擬及分析解決方案的效能與整合度天花板。 你將負責： 設計SoC系統架構和功能分割，定義數位與類比功能區塊 開發SoC內部互連架構和資料流路徑最佳化方案 協調數位IC和類比IC的功能整合與系統驗證 建立SoC設計流程並進行系統效能與功耗優化 我們期待你具備： 碩士以上學歷，熟悉完整SoC設計流程（規格→架構→實現→驗證） 精通SoC系統架構設計（CPU/DSP、記憶體階層、匯流排架構、電源管理） 熟悉RTL設計、SystemVerilog/VHDL與SoC驗證方法學（UVM等） 具備SystemC、MATLAB/Simulink系統建模與EDA工具鏈操作能力 加分條件： 有電力電子、電源管理或混合信號SoC整合經驗 熟悉DSP或專用處理器架構設計 具備先進製程節點（28nm以下）設計考量經驗 有成功的SoC tapeout和量產經驗 如果你熱愛用系統整合重新定義電力分析晶片的可能性，歡迎加入我們，打造更智慧的硬體未來！

【工作內容】 • Work with team members and apply current functional verification techniques to perform and improve pre-silicon verification quality and product Time to Market • Provide the technical leadership to the DV team for the project • Work independently on various DV tasks and provide technical guidance to the DV team. • Be involved technically in the porting/creation of the DV environment for the new design, block and chip level test plan creation and implementation, coverage analysis, and regression cleanup 【職務條件】 • Master’s degree in Electrical Engineering, Computer Science, or related. • Good understanding of ASIC design verification flow. • RTL coding with Verilog/System Verilog and familiar with front-end design flow and C/C++ programming experiences. • Knowledge of Perl, OVL, SVA, SV, UVM, OVM, script programming, etc. 【其他條件】 • MSEE with a minimum of 5 years, or BSEE with a minimum of 8 years of experience in digital ASIC/SOC design verification • MS/BS degree in EE or CS with expertise in digital IP/SOC design verification.

1. Verilog or VHDL程式經驗 2. 應用FPGA之功能設計

工作描述 - 跟據IP 需求制定硬件架構及硬件功能列表 - 跟架構、物理實現以及芯片驗證團隊一起合作去交付滿足功能/時序/功耗要求的設計，並協助流片前跟流片後的問題分析 - 交付SOC設計項目的RTL/SDC/UPF 設計 崗位要求 - 碩士以上，年資不限，電機、自動控制、電子、機械相關科系畢業為主 - 有好的溝通能力，能流暢的描述設計思想跟討論問題 - 有強烈的學習熱忱，對技術理論能有好奇心以及自趨力去成長

【About Us】 VICI Holdings' Hardware team is seeking a Senior Digital Design Engineer to join our dynamic group. In this role, you will be pivotal in advancing our trading systems, contributing to the development and enhancement of cutting-edge technologies. We boast the leading digital hardware development team in Taiwan and possess FPGA design technology in parallel with wall street trading firms. This expertise enables us to build ultra-low-latency, fully automated trading systems. Our trading strategies cover stocks, futures, and derivatives, achieving a daily global trading volume in the hundreds of millions dollars. 【Roles/ Responsibilities】 • Micro-architecture, design and implement high-performance digital circuits optimized for low-latency application • Develop high speed data paths, ensuring minimal logic depth and efficient pipeline • Optimize critical paths and combinational logic to reduce propagation delays and improve throughput • Work with Verilog/ SystemVerilog to implement RTL design • Apply parallelism and resource sharing techniques to enhance performance and throughput • Develop latency-aware micro-architectures for real-time processing and networking applications • Debug, optimize and iterate on designs using FPGA platform and cycle-accurate simulation • Work closely with digital/system verification engineers to ensure functional correctness and performance validation • Take ownership of FPGA verification tasks to ensure design correctness and performance. • Develop and execute verification plans for high-speed IPs such as PCIe, Ethernet, and Switches. • Support system validation engineer to debug FPGA issue Design Collaboration: • Collaborate closely with Algorithm, software, design validation and application team to define micro-architecture Performance Analysis: • Conduct performance testing and analysis, ensuring the low-latency goals are met across various use cases. • Capability to solve routing timing issue and analysis FPGA timing report result. 【Candidate Requirements】 • Master’s degree or above in EE, CE, or CS, plus 3–8 years of high-speed digital-design experience • Hands-on experience in IP-level digital-circuit design or IP integration (preferred) • Proficient in debugging and optimization with VCS and Verdi simulation tools • Comfortable working in Linux/Unix environments • Strong analytical and problem-solving skills with a performance-driven mindset 【Other Requirements】 • Proven ability to solve complex design challenges and deliver robust solutions • Experience designing ultra-low-latency data paths—arithmetic units, multiplexers, FIFOs, registers—for high-performance applications (preferred) • Familiarity with FPGA verification tools such as Quartus or Vivado (a plus) • Knowledge of high-bandwidth memory interfaces (DDR, HBM, etc.) • Understanding of networking protocols (Ethernet, PCIe, etc.) 【Interview Process】 • Resume Screening → HR Phone Screen → Face-to-Face Interview (with 30-60mins on-site coding test)

1.Work with team members and apply design techniques to work on different phases of complex logic design for ASIC/SOC project. 2. Working on the following tasks from time to time: HDL coding, documentation, RTL quality check, cooperate with back-end engineer etc.

DRAM數位邏輯電路設計 『具工作經驗者，薪資另議』

1. 負責數位IC設計整合: a. 依客戶需求設計整合IC功能、工作頻率、介面規格、消耗功率等基本規格 b. 完成SoC系統架構設計，並依功能單元運作屬性區分區塊規格 c. 使用Verilog/VHDL編程內部功能並撰寫RTL code 2. 負責功能驗證與除錯 a. 制定功能驗證計畫 b. 審核驗證計畫的完整性和正確性 c. 進行基本模擬，確認RTL code的功能 d. RTL code寫入FPGA晶片連接系統測試，驗證RTL code 3. 負責時序分析與功耗管理 a. 產出邏輯閘級電路連線網表(netlist) b. 進行SoC系統的時序分析 c. 進行SoC系統的功耗分析 4. 其它主管交辦事項 【必要條件】 1. 電機、電子、資訊工程或相關科系，碩士以上學歷 2. 三年以上 SoC 設計或整合經驗 3. 熟悉CPU子系統設計整合 a. 熟悉 ARM 架構， b. 對 RISC-V 架構有基本認識 4. 熟悉數位IC前端設計流程，如RTL design、Lint/CDC、Synthesis、STA、LEC、ECO等 5. 具類比IP整合相關經驗，例如PHY、Serdes、PLL等 6. 熟悉IC後段設計流程，如DFT、MBIST、P&R、post-cilicon system level debugging等

1.Work with Hardware, BIOS ,BMC, and Firmware team for CPLD design, validation, and maintenance 2.Develop Server production power on sequence control logic by CPLD / FPGA 3.Implement new technology and design concept in CPLD / FPGA Design test plan, development specification, and issue tracking.

1. Development of ASIC verification plans. 2. Development of UVM tests for ASIC verification to achieve comprehensive coverage. 3. Working with ASIC design and architecture teams to understand functionality. Requirements : 1. Bachelor’s degree in Electrical Engineering or Computer Science. 2. Knowledge of HDL and experience in behavioral and RTL coding, Verilog preferred. 3. Knowledge of ARM AMBA Bus protocols 4. Knowledge of System Verilog and UVM verification methodology. 5. Four-year (Master) or six-year (Bachelor) experiences on design verification with UVM platform.

Overview We are seeking a highly skilled FPGA Engineer to architect and implement high-performance digital logic for next-generation camera platforms. This role is pivotal in enabling real-time video processing and efficient sensor integration. Key Responsibilities Design & Implement Camera Interfaces: Develop FPGA logic to handle high-speed camera data streams (e.g., MIPI, LVDS, CSI). Real-Time Image Processing: Integrate or design FPGA IP cores for image signal processing, filtering, and feature extraction. Sensor Synchronization: Ensure precise timing between multiple camera modules and other sensor inputs. Latency Optimization: Optimize FPGA architectures for low-latency video capture and data throughput. Verification & Testing: Create simulation testbenches and perform hardware-in-the-loop testing for camera pipelines. Collaboration: Work closely with camera hardware and system integration teams to define requirements and validate performance.

本職位是公司數位IC設計團隊負責開發和驗證mini-LED, uLED相關設計，具重要發展前景 1. 負責Controller/Image IP 相關數位電路開發與驗證; 2. LED 驅動控制IP開發,維謢； 3. NAND flash控制IP開發,維謢； 4. 數位IP FPGA驗證； 如果您符合以上要求，請儘快投遞履歷表，我們期待您的加入！

1. FPGA加速應用系統整合開發與驗證 2. IP開發/驗證/整合 3. 產品除錯與分析支援

RTL,APR,TEST,AP

About us: VICI Holdings' Hardware team is seeking a skilled FPGA Engineer to join our dynamic group. In this role, you will be pivotal in advancing our trading systems, contributing to the development and enhancement of cutting-edge technologies. We boast the leading software development team in Taiwan and possess FPGA design technology in parallel with wall street trading firms. This expertise enables us to build low-latency, fully automated trading systems. Our trading strategies cover stocks, futures, and derivatives, achieving a daily global trading volume in the hundreds of millions dollars. Roles/ Responsibilities: • High speed IP interface design (such as PCIE gen 3, 4 / Ethernet, DDR etc.) • In charge of FPGA design/ implementation/simulation. • Transmission protocol layer development. • Optimizing hardware for latency. • Proficiency with Xilinx design environment. Candidate Requirements: • BS/MS degree above from EE, CE with 2+ years of relevant work experience • Experience in high-speed interface design or knowledge in PCIE/ Ethernet/MIPI/DDR design or implementation is a plus • Experience using System Verilog and at least two prior RTL design is a required. • Demonstrated ability to tackle complex design challenges and implement effective solutions Other Requirements: • High self-motivated individual with good communication skill. • English level – working level proficiency is a plus. Interview Process: • Resume selection ->Coding Test -> AI Interview (Online) -> F2F Interview -> HR Manager

1. CPLD/FPGA 經驗 Verilog、VHDL 程式編輯經驗 2. X86 ARM 架構 CPLD 設計經驗 3. 硬體設計架構系統規劃 4. 獨立專案作業能力佳 5. Module code 組織編輯能力 *歡迎對verilog coding有興趣者投遞，公司將依學經歷、能力核敘

1.客戶FPGA and SoC 技術相關問題處理 2.FPGA and SoC 設計技巧教育訓練 3.Xilinx 產品推廣

1. 主動式電子掃描陣列 (相控陣列) 雷達系統之數位控制。 2. 熟悉Verilog與FPGA開發流程，了解High-Level Synthesis開發技術。 3. 具有實作數位訊號處理與數位架構設計於FPGA之經驗。