「APR Engineer (Implementation Engineer)」的相似工作

1. ARM CPU design physical implementation 2. ARM CPU power and timing sign off 3. Physical design flow enhancement for high-speed CPU

我們正在尋找一位熱情、有經驗的EDA應用工程師，加入我們充滿創新和技術挑戰的團隊。這位工程師將與台灣地區的客戶及合作夥伴緊密合作，提供最新的電子設計自動化工具和技術支援，以實現客戶的設計最佳化及效率提升。 職責： 與客戶端的工程師密切合作，了解其設計需求，提供EDA工具相關的技術支援。 協助客戶優化和自動化設計流程，以提高生產力和效率。 在EDA工具中執行模擬和分析，確保客戶設計的性能、功耗和可靠性符合要求。 解決客戶在設計過程中遇到的技術挑戰，提供解決方案以滿足其產品開發目標。 資格要求： 學士或以上學歷，專業領域包括電子工程、計算機工程或相關領域。 具備良好的問題解決和溝通能力，能夠有效協作並在客戶團隊中發揮領導力。 對IC設計、半導體及EDA產業有濃厚興趣，並追求不斷學習和專業成長。 必要條件： 具有相關EDA工具（如Cadence、Synopsys、Mentor Graphics等）的使用經驗。 熟悉硬體描述語言（SystemVerilog、Verilog、VHDL）和模擬工具。 英文聽說讀寫中等以上

1. Work on 3~7nm design implementation, methodology, and sign-off 2. Perform synthesis, DFT, floorplan, clock planning, place and route, timing closure, ECO, IR signoff, and physical verification 3. Manage schedule, resolve design and flow issues, drive methodologies and execution

Responsibilities: • Develop integrated verification environment. • Verify designs with system verilog and system verilog assertion. • Build, maintain and upgrade testbenches and their components using UVM-based methods. • Check functional coverage and code coverage • Create controlled random testcases. Pre-debug and provide debug reports. • Scripting experience using scripting languages like Perl and Python.

1. Front-end IC design flow development/maintain/support 2. Experience in front-end design flow and familiarity with Prime Time,Prime Closure,Fusion Compiler. 3.Good understanding of timing sign off,constraint and timing closure methodology.

主要職責 1. Layout設計與實作 根據電路圖（schematic）進行analog/mixed-signal或digital layout佈局設計 執行模組層級（block-level）與頂層（top-level）layout整合 負責元件placement、routing、floorplan與metal layer規劃 2. DRC/LVS檢查與修正 使用EDA工具執行設計規範檢查（DRC, LVS） 修正版圖與設計間的不一致，確保layout正確無誤 執行ERC（Electrical Rule Check）、ANT（Antenna Check）等檢查 3. 協同工作與設計優化 與電路設計工程師合作進行版圖最佳化（例如降低parasitics、改善matching） 針對layout提出建議以達到功耗、面積與性能的最佳平衡 4. 製程與封裝考量 根據製程規範（Design Rule）進行設計，考量DFM（Design for Manufacturability）與封裝需求 了解不同foundry的PDK（Process Design Kit）限制與應用

【主要工作內容】 1.Netlist to GDS, including floorplan/powerplan/physical synthesis/clock tree synthesis & routing 2.Chip level physical verification, including DRC/LVS/DFM & tapeout 3.IR-Drop analysis 【需求條件】 1.有使用過ICC/ICC2/laker, 曾做過fully layout & chip level PV 2.工作態度積極認真, 有獨自解決問題能力

1. Design verification with SystemVerilog/UVM, C/C++ 2. Integration test environment with VIP 3. Develop checker and scoreboard. 4. Verify design with SystemVerilog assertion. 5. Test plan for a verification task. [Requirement] 1. Familiar with SystemVerilog HDL, OOP, Python, TCL, and shell programming. 2. Better to have SoC design and bus concept.

Introduction to the job Do you like challenges and do you want to work in a fast pacing supply chain environment to support some of the biggest semiconductor companies worldwide? Are you familiar with Logistics Operations and like to managing urgent demands on a daily basis?  If this sounds like you and if you have a strong customer oriented mindset, here is your mission. Role and responsibilities For our Global Operations Center in Taiwan we are searching for Supply Chain Professionals. You fulfill the demand of our customers for spare parts and tools for their maintenance activities on some of the most complex machines in the right quantity and at the right time & cost. Time is of the essence to ensure a seamless production of our customers without interruptions on our machines. -Handling of urgent material requests from worldwide customers in a rolling 24/7 shift system with the right customer focus, while meeting all milestones related to communication and execution -Monitoring of worldwide shipments  -Ability to resolve complex issues and drive improvements to further optimize processes -Ability to support escalations and provide communication proposals for review -Constructive and reliable communication with worldwide stakeholders from all departments within ASML -This position requires shift work. Education and Experience Bachelor's Degree in related subject i.e. Supply Chain Management, Information Science, Engineering etc. preferred -Minimum 1 year of relevant experience in an international company, semiconductor industry is preferred -A tactical thinker with strong interpersonal and communication skills -Analytical thinking and ability to organize and prioritize workload Skills Working at the cutting edge of tech, you’ll always have new challenges and new problems to solve – and working together is the only way to do that. You won’t work in a silo. Instead, you’ll be part of a creative, dynamic work environment where you’ll collaborate with supportive colleagues.  There is always space for creative and unique points of view. You’ll have the flexibility and trust to choose how best to tackle tasks and solve problems. To thrive in this job, you’ll need the following skills: -Stress-resistant; act under high pressure -Flexible; willing to go the extra mile for the customer -Excellent professional communication in English, written and oral -Drive for results; does not stop until solution has been found, even when obstacles arise -Team player -Change management competencies -Convincing, pro-active and “can do” mentality -Cultural awareness -Experience with ERP system(s), SAP R/3 knowledge preferred -Ability to prioritize Diversity and inclusion ASML is an Equal Opportunity Employer that values and respects the importance of a diverse and inclusive workforce. It is the policy of the company to recruit, hire, train and promote persons in all job titles without regard to race, color, religion, sex, age, national origin, veteran status, disability, sexual orientation, or gender identity. We recognize that diversity and inclusion is a driving force in the success of our company. Need to know more about applying for a job at ASML? Read our frequently asked questions.

1. SerDes CTRL IP RTL 開發與維護 (例如LPDDR､UFS､NAND Controller...) 2. 設計驗證 3. FPGA相關設計與實作 以上工作依個人意願酌情分配

【工作內容】 • Work with team members and apply current functional verification techniques to perform and improve pre-silicon verification quality and product Time to Market • Provide the technical leadership to the DV team for the project • Work independently on various DV tasks and provide technical guidance to the DV team. • Be involved technically in the porting/creation of the DV environment for the new design, block and chip level test plan creation and implementation, coverage analysis, and regression cleanup 【職務條件】 • Master’s degree in Electrical Engineering, Computer Science, or related. • Good understanding of ASIC design verification flow. • RTL coding with Verilog/System Verilog and familiar with front-end design flow and C/C++ programming experiences. • Knowledge of Perl, OVL, SVA, SV, UVM, OVM, script programming, etc. 【其他條件】 • MSEE with a minimum of 5 years, or BSEE with a minimum of 8 years of experience in digital ASIC/SOC design verification • MS/BS degree in EE or CS with expertise in digital IP/SOC design verification.

[job description] Wolley is seeking candidates for a digital design engineer position. You will join an experienced team designing next-generation memory, storage controllers, and high-speed interface standard. You will also contribute to design concept discussion, architecture definition, as well as design implementation. ‧ Architecture design and RTL implementation ‧ System bus and related peripheral designs ‧ SoC and emulation platform design ‧ SoC system performance analysis [Requirement] 1. Bachelor's or Master's degree in Electrical Engineering or related fields 2. Familiar with RTL design, SystemVerilog, front-end design flow 3. The following working knowledge is desired: * Python programming * TCL scripting * Universal Verification Methodology (UVM) * Low power design and analysis

DESCRIPTION: 1. Responsible for the physical design process of chip numbers from netlist to GDSII 2. Responsible for interaction with the front-end design team to realize the design convergence and optimization of the front and back ends; Comprehensive, static timing analysis 3. Floor planning, power planning and signoff, place and route, timing closure, chip static timing analysis and physical verification 4. IP integration, synthesis, verification and correction 5. Other Assigned Tasks delivered by the Line Manager QUALIFICATIONS: 1. MS degree in EE or related. 2. Familiar with physical design flow, including hierarchical design and low power design is a plus 3. Familiar with EDA tools, such as SoC Encounter/INNOVUS/ICC/ICC2 is a plus 4. Familiar with computer languages such as Perl/TCL/C-shell 5. Self-motivated with good communication skills and team spirit 6. Ability to understand and articulate technical issues. 7. Fluent English is a plus. 8. Experience in 12/5nm design is a plus.

1. Knowledge and experience of circuit design guideline, latch up, EM and ESD checking rule. 2. Calibre DRC/LVS/PERC Command File maintain and writing. 3. Physical Verification flow enhancement and deployment. 4. CAD Utility development. 5. Soft skill ability like TCL, Perl, shell script

Job Description: In this position the individual will develop test environment, test plan, and test cases based on the product specification and related industrial standards. The individual will require initiating a test plan review with the team and updating the test plan accordingly. The candidate will require executing and developing the test cases based on test plan, debugging and reporting the test result to achieve full function coverage goal. The individual will require developing ASIC bench functional test programs and doing ASIC bring-up and ASIC bench testing. The ideal individual must have proven ability to achieve results in a fast moving, dynamic environment. The candidate must have ability to coordinate priorities and initiatives and clear communication skill.

1. 主動式電子掃描陣列 (相控陣列) 雷達系統之數位控制。 2. 熟悉Verilog與FPGA開發流程，了解High-Level Synthesis開發技術。 3. 具有實作數位訊號處理與數位架構設計於FPGA之經驗。

1. 具備 Layout 工作經驗，想挑戰SOC晶片(Mix mode / HV / SRAM / Power / ESD..)並有志往Physical design 發展者 2. 需懂ESD / 製程觀念 / 電路原理 3. 具Tapeout 量產經驗，獨立處理 Whole chip 能力尤佳 4. 熟以下流程尤佳：Laker L3+ HSIM simulation + IREM分析 5. 強烈要求穩定性高，積極度高，做事態度需具備高度 Commitment 決心與毅力，具備高度 EQ/AQ，擁有團隊合作的精神 6. 工作地點：此職缺在【台南(樹谷園區)、新竹】皆設有相關單位。

使用最新的IC驗證方法對晶心的CPU設計做高強度測試，以提升CPU設計的品質與完整度。此職務可以累積對計算機架構，微架構，與嵌入式系統的廣泛知識。具體內容包含: * Understanding uarch of Andes processor designs * Creating verification plans * Implementing test environments * Generating test cases * Improving test coverage * Identifying CPU bugs in various environments (simulation, FPGA, etc.) * Test automation * Performance benchmarking

【成為円星人】 円星科技由一群專業與充滿熱情的夥伴創立於2011年，為積體電路矽智財設計服務業之新秀，秉持著『成為半導體業最值得信賴之IP公司』的願景，追求永續經營與成長。 誠摯歡迎您成為円星人，加入我們，站上國際舞台！ 一起共同打拚，以精品文化之精神，創造價值，追求卓越！ 【職務簡介】 M31主要業務為向 IC 設計業者和晶圓代工廠授權 IP，此職務為負責IO電路設計相關之職缺。 【將負責的工作內容】 1. ESD/Latch-up防護設計與驗證 2. I/O電路設計 (Fail safe, Tolerant, Cascade) 3. 高速IO 電路設計 (DDR, ONFI, SDIO) 4. LDO/POR/VDT 電路設計 5. XTAL oscillator 電路設計 6. Analog circuit, IO, PISI, ESD Basic/Advanced Knowledge 【條件與特質】 1. Analog circuit, IO circuit design and simulation 2. 擅長工具-SPICE, Virtuoso 3. 有IO 相關工作經歷3年以上, Analog/IO Basic/Advanced Knowledge 如果您有以上相關經驗且對此職缺有興趣，歡迎投遞您的履歷！

【本職缺優先審核至高通官網投遞人選】請至高通官網上傳英文履歷表https://careers.qualcomm.com/careers/job/446705989572 【Talents who apply job through Qualcomm Career Website will be reviewed and considered as top priority】 https://careers.qualcomm.com/careers/job/446705989572 【General Summary】 As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm CPU Engineer, you will lead innovative Central Processing Unit (CPU) design efforts that have a critical impact on industries across the world. Qualcomm Engineers collaborate with cross-functional teams to design, verify, and implement multi-core CPU operations for all Qualcomm Business Units. 【Roles and Responsibilities】 • Collaborate with cross-functional teams (RTL, Physical Design, Circuits, CAD) to address critical physical design challenges in CPU implementations. • Develop innovative techniques within Physical Design and optimization space to meet stringent PPA targets. • Coordinate with CPU Software, Architecture, and RTL teams to understand various CPU use cases and propose impactful PPA optimizations. • Engage with external CAD tool vendors and internal CAD teams to identify and enhance optimization issues related to CPU designs. • Partner with all block-level implementation teams to analyze, implement, and improve optimization methods relevant to the designs. • Partner with Process, SoC and Post-silicon teams to analyze, improve design implementations. 【Must have skill/experience】 • Experience with Synthesis, place and route and signoff timing/power analysis. • Knowledge of high performance and low power implementation techniques • Proficiency in scripting (TCL, Python, Perl) 【Minimum Qualifications】 • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 6+ years of Hardware Engineering, Electrical Engineering, or related work experience. OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 4+ years of Hardware Engineering, Electrical Engineering, or related work experience. OR PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field and 3+ years of Hardware Engineering, Electrical Engineering, or related work experience.