「APR Engineer (Implementation Engineer)」的相似工作

Responsibilities: • Develop integrated verification environment. • Verify designs with system verilog and system verilog assertion. • Build, maintain and upgrade testbenches and their components using UVM-based methods. • Check functional coverage and code coverage • Create controlled random testcases. Pre-debug and provide debug reports. • Scripting experience using scripting languages like Perl and Python.

1. 負責後段APR flow 　 Familiar Netlist-to-GDS Design flow. Including,Floorplan/Power Plan/IR drop analysis、Placement/CTS/Route、Timing Analysis . 2. Physical Verification. Including, -DRC/LVS to tapeout. 3. 負責與客戶做設計服務的技術討論 4. 作為Project leader與APR團隊合作完成專案 5. 對IP survey有一定程度的了解為佳

1.Support and maintain EDA tools and flows used in the digital IC implementation. 2.Design and develop methodologies, automation scripts, and design flow. 3.Manage version control system (Git/SVN), issue tracking system, and CI/CD flow. [Requirement] 1.Python/Perl/TCL/Shell programming skills. 2.Familiar with EDA tools for IC design flow. 3.Basic knowledge of Verilog or SystemVerilog HDL.

Job Description: In this position the individual will develop test environment, test plan, and test cases based on the product specification and related industrial standards. The individual will require initiating a test plan review with the team and updating the test plan accordingly. The candidate will require executing and developing the test cases based on test plan, debugging and reporting the test result to achieve full function coverage goal. The individual will require developing ASIC bench functional test programs and doing ASIC bring-up and ASIC bench testing. The ideal individual must have proven ability to achieve results in a fast moving, dynamic environment. The candidate must have ability to coordinate priorities and initiatives and clear communication skill.

1. Design verification with SystemVerilog/UVM, C/C++ 2. Integration test environment with VIP 3. Develop checker and scoreboard. 4. Verify design with SystemVerilog assertion. 5. Test plan for a verification task. [Requirement] 1. Familiar with SystemVerilog HDL, OOP, Python, TCL, and shell programming. 2. Better to have SoC design and bus concept.

(1)Circuit Design. (2)Circuit Simulation. (3)Layout Verification. (4)Silicon verification and debugging. (5)Transfer design to production.

主要職責 1. Layout設計與實作 根據電路圖（schematic）進行analog/mixed-signal或digital layout佈局設計 執行模組層級（block-level）與頂層（top-level）layout整合 負責元件placement、routing、floorplan與metal layer規劃 2. DRC/LVS檢查與修正 使用EDA工具執行設計規範檢查（DRC, LVS） 修正版圖與設計間的不一致，確保layout正確無誤 執行ERC（Electrical Rule Check）、ANT（Antenna Check）等檢查 3. 協同工作與設計優化 與電路設計工程師合作進行版圖最佳化（例如降低parasitics、改善matching） 針對layout提出建議以達到功耗、面積與性能的最佳平衡 4. 製程與封裝考量 根據製程規範（Design Rule）進行設計，考量DFM（Design for Manufacturability）與封裝需求 了解不同foundry的PDK（Process Design Kit）限制與應用

1. Front-end IC design flow development/maintain/support 2. Experience in front-end design flow and familiarity with Prime Time,Prime Closure,Fusion Compiler. 3.Good understanding of timing sign off,constraint and timing closure methodology.

【工作內容】 • Work with team members and apply current functional verification techniques to perform and improve pre-silicon verification quality and product Time to Market • Provide the technical leadership to the DV team for the project • Work independently on various DV tasks and provide technical guidance to the DV team. • Be involved technically in the porting/creation of the DV environment for the new design, block and chip level test plan creation and implementation, coverage analysis, and regression cleanup 【職務條件】 • Master’s degree in Electrical Engineering, Computer Science, or related. • Good understanding of ASIC design verification flow. • RTL coding with Verilog/System Verilog and familiar with front-end design flow and C/C++ programming experiences. • Knowledge of Perl, OVL, SVA, SV, UVM, OVM, script programming, etc. 【其他條件】 • MSEE with a minimum of 5 years, or BSEE with a minimum of 8 years of experience in digital ASIC/SOC design verification • MS/BS degree in EE or CS with expertise in digital IP/SOC design verification.

1. Knowledge and experience of circuit design guideline, latch up, EM and ESD checking rule. 2. Calibre DRC/LVS/PERC Command File maintain and writing. 3. Physical Verification flow enhancement and deployment. 4. CAD Utility development. 5. Soft skill ability like TCL, Perl, shell script

1.電子相關領域佳 大學/碩士 ,Fully IC Layout工作經驗尤佳 2.需修過VLSI設計概論、半導體器件等相關課程，熟VLSI設計，懂類比設計，半導體元件物理尤佳 3.對於IC設計後段 , Physical Design 領域有濃厚興趣者，懂IR-Drop/EM analysis，或有興趣者尤佳 4.對於 Parasitical device effect prevent, ESD/EMI physical design , HV Design/Layout , IC Layout Reliability有濃厚興趣者 5.此職務需要穩定性高，積極度高，做事態度需細心嚴謹 , 需具備高度 EQ/AQ，擁有團隊合作的精神 6.對高複雜度的Whole chip 整合有興趣者

Design CPU functional units. Responsibilities  Defining micro-architecture of the functional units  Writing RTL codes of the functional units  Writing documents of the function units  Working with cross-division teams to resolve functional, performance, power, and frequency issues related to the functional units Qualifications  Available to start work three months after being hired.  3+ years of recent experience with Verilog logic design  Knows CPU micro-architecture, e.g. instructions, pipeline, caches, MMU  Knows power consumption of digital circuits  Good communicator in verbal and writing in English

Job Description We are seeking a highly skilled ASIC Verification Engineer to join our team in Chupei, Taiwan. In this role, you will be responsible for developing and implementing comprehensive verification strategies for complex ASIC designs, ensuring the highest quality and reliability of our semiconductor products. Develop and execute verification plans for complex ASIC designs Create and maintain testbenches using SystemVerilog and UVM Design and implement efficient verification environments Perform functional and formal verification of digital designs Develop automated test scripts to improve verification efficiency Analyze and debug design issues identified during verification Collaborate with design engineers to resolve functional discrepancies Generate detailed verification reports and documentation Stay updated with industry trends and emerging verification methodologies Contribute to the continuous improvement of verification processes and tools Qualifications Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field 5+ years of experience in ASIC verification with strong proficiency in SystemVerilog and UVM Experience with Verilog, VHDL, and industry-standard simulation tools (e.g., Synopsys VCS, Cadence Xcelium) Experience of CPU, GPU, NPU or HBM verification Knowledge of formal verification techniques and tools Strong debugging, problem-solving, and analytical skills Solid understanding of digital logic design, computer architecture, and communication protocols Excellent organizational skills with strong attention to detail Good communication and teamwork skills in a fast-paced environment

擴大規模，大量徵才 1.專業Full Custom IC layout 2.對IC Layout 有興趣者, 須具有清晰之 邏輯觀念

Please apply this role through https://careers.synopsys.com/job/hsinchu/r-and-d-engineering-sr-staff-engineer/44408/84900058096 Synopsys is looking for motivated Product Engineer to help design, develop and test state of the art Static Timing, Characterization and Library modelling tools. The primary focus of the Product Engineer is closely working with R&D team, to influence technologies/solution roadmaps and provide R&D team with accurate input from Field AEs, helping them focus on the most critical design challenges and help define solutions to critical problems. The engineer will work closely with Field AEs, ensuring overall consistency of end-to-end design and analysis flow to meet customer needs. The engineer will also work with Sales and Marketing teams to find and develop new markets, drive new tool evaluations and help customers with the adoption and continuous usage of Static Timing, Characterization and Library Modelling, thus enabling Chip Design customers achieve best Timing, Power and Characterization Goals. Synopsys’ existing and forthcoming tools offer an advanced transistor-level static timing characterization and library modelling solution that addresses the existing and emerging challenges in custom and memory design. They offer predictability and improved productivity to designers. Their concurrent timing, SI features and advanced variation aware analysis enables designers to accurately and quickly identify design issues early-on and avoid expensive late-finding of problems in silicon. Main responsibilities: • Drive new products and new product features that exceed customer needs. • Work with RnD to enable timely implementation of new products and features, and important bug fixes. • Provide consultation to prospective users and/or product capability assessment and validation. • Provide tool trainings to customers and Field AEs. • Provides technical expertise to sales staff through sales presentations and product demonstrations. • Assists the sales staff in assessing potential application of company products to meet customer needs and preparing detailed product specifications for the development and implementation of customer applications/solutions. Requirements: We are looking for an innovative, motivated, and dependable person, with at least BS degree and 8+ years of recent hands-on experience including: · Exceptional expertise in transistor-level analysis and debug circuit level issues for SRAM, RF, ROM memories and Standard Cells. · Good exposure to static timing concepts and CMOS engineering fundamentals. · Good knowledge of TCL and or other scripting languages. · Very good communication, social and leadership skills. Plus: · NanoTime or PrimeLib experience highly desirable.

1. 熟讀規格書，建立VPLAN 2. 使用SystemVerilog 程式語言設計，UVM 建立模擬環境 3. 執行CRT驗證流程 (使用使用VERDI VCS NC等工具) 4. 跨部門合作溝通 (設計&軟體等部門)

DESCRIPTION: 1. Responsible for the physical design process of chip numbers from netlist to GDSII 2. Responsible for interaction with the front-end design team to realize the design convergence and optimization of the front and back ends; Comprehensive, static timing analysis 3. Floor planning, power planning and signoff, place and route, timing closure, chip static timing analysis and physical verification 4. IP integration, synthesis, verification and correction 5. Other Assigned Tasks delivered by the Line Manager QUALIFICATIONS: 1. MS degree in EE or related. 2. Familiar with physical design flow, including hierarchical design and low power design is a plus 3. Familiar with EDA tools, such as SoC Encounter/INNOVUS/ICC/ICC2 is a plus 4. Familiar with computer languages such as Perl/TCL/C-shell 5. Self-motivated with good communication skills and team spirit 6. Ability to understand and articulate technical issues. 7. Fluent English is a plus. 8. Experience in 12/5nm design is a plus.

## 職務說明 - 應用於無人機雷達系統 - 數位IP架構設計與實作。 - 透過MATLAB/C++協助數位IP驗證 - 透過FPGA整合與驗證。 ## 技能要求 - 具備數位訊號處理經驗 - 具備數位電路設計經驗 - 程式語言必要：Verilog/VHDL, TCL, ##加分條件： - 具備雷達/通訊訊號處理、數位設計架構 - 具備RF/Analog 知識與RF/Analog校準設計 - 程式語言: MATLAB, python, c, c++, Chisel3

1. ARM CPU design physical implementation 2. ARM CPU power and timing sign off 3. Physical design flow enhancement for high-speed CPU

1.Analog & physical design flow/script development 2.IR/EM sign-off 3.Flip-chip design 4.Physical verification flow