「資深APR工程師」的相似工作

1. 負責後段APR flow 　 Familiar Netlist-to-GDS Design flow. Including,Floorplan/Power Plan/IR drop analysis、Placement/CTS/Route、Timing Analysis . 2. Physical Verification. Including, -DRC/LVS to tapeout. 3. 負責與客戶做設計服務的技術討論 4. 作為Project leader與APR團隊合作完成專案 5. 對IP survey有一定程度的了解為佳

DESCRIPTION: 1. Responsible for the physical design process of chip numbers from netlist to GDSII 2. Responsible for interaction with the front-end design team to realize the design convergence and optimization of the front and back ends; Comprehensive, static timing analysis 3. Floor planning, power planning and signoff, place and route, timing closure, chip static timing analysis and physical verification 4. IP integration, synthesis, verification and correction 5. Other Assigned Tasks delivered by the Line Manager QUALIFICATIONS: 1. MS degree in EE or related. 2. Familiar with physical design flow, including hierarchical design and low power design is a plus 3. Familiar with EDA tools, such as SoC Encounter/INNOVUS/ICC/ICC2 is a plus 4. Familiar with computer languages such as Perl/TCL/C-shell 5. Self-motivated with good communication skills and team spirit 6. Ability to understand and articulate technical issues. 7. Fluent English is a plus. 8. Experience in 12/5nm design is a plus.

1. 負責 Android ARM 平台系統整合。 2. 與跨部門軟體開發人員緊密合作，推動專案按時交付。 3. 分析和解決系統整合過程中出現的技術問題。 4. 配合測試人員進行調試工作。 5. 專案代碼管理與維護。

Position Description Develop PEGASUS/PVS DRC, FILL, LVS, LPE rule decks and RCX flow for worldwide foundries. Manage onsite technical qualification to ensure both PEGASUS/PVS decks and tools are officially qualified by foundries. Collaborate closely with early adoption customers to track and resolve product issues Establish communication channels with R&D to capture customer needs and requirement spec. Work with R&D to enhance and improve PEGASUS/PVS, positioning it as a leading edge Physical Verification tool Position Requirements B.S. in Electrical Engineering (EE), Computer Science (CS), or related area (or equivalent) and 3 - 5 years of experience with Physical Verification tool support/development OR M.S. in EE or CS, or related area (or equivalent) and 1 - 3 years of experience with Physical Verification tool support/development Profound knowledge with Foundry Design Rules and semiconductor fabrication process Ability to develop PEGASUS/PVS rule deck for worldwide foundries, ensuring quality, performance, and compliance with schedules and qualification requirements. Proficiency in TCL and PERL scripting is required Strong English communication skills. Software development experience preferred; familiarity with Cadence SKILL programming is a plus. Experience with IC design and CAD support is advantageous.

【本職缺優先審核至高通官網投遞人選】請至高通官網上傳英文履歷表:https://qualcomm.wd12.myworkdayjobs.com/External/job/Hsinchu-City-TWN/Custom-Design-Automation-Engineer-EM-IR-Flows_3078527 General Summary: In this highly cross functional role, you will be part of the Global Design Enablement team responsible for various aspects of Design Automation and flow development across Custom, Analog and RF technology nodes. As a member of the CAD team, you will be working closely with the Engineering design community to develop & support transistor level EM/IR tools and flows including Circuit Simulation and IP characterization. You will also have the responsibility to collaborate with our Foundry and EDA partners to deploy best-in class EDA tools and flows in addition to developing in-house productivity & QoR automation solutions for improving overall design methodology. Preferred Qualifications: Bachelors or Masters in Electrical Engineering, Computer Engineering, or related field. 6+ years of industry experience in Design Automation involving Transistor level EM/IR Analysis and/or methodology development Knowledge of Virtuoso suite of tools – Schematic, Layout, Analog Design Environment, post-layout simulations etc. Excellent in debugging spice netlist and simulator issues Good understanding of CMOS fundamentals, physical layout and basic Circuit Design Concepts Strong aptitude for programming and automation with proficiency in one or more of the programming/scripting languages – Python, Perl, SKILL and TCL. Good English communication skills and ability to work collaboratively in a team environment Experience with EM/IR tools, like Totem, Voltus-fi, CustomSim-RA , either as an advanced user or as a flow developer. Familiarity with SPICE simulation tools (Hspice, SpectreX/APS, AFS/Solido SPICE , PrimeSim SPICE, ADS, GoldenGate etc.) Knowledge of FinFet & 3dic is a plus Minimum Qualifications: Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience. OR Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience. OR PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.

1. ARM, RISC-V平台應用規劃、開發 2. 新一代PPU 規劃開發 3. 熟悉微處理器系統架構 (MCU、ARM、RISC-V) 4. 熟悉C、C++、Assembly 5. 熟悉數位邏輯

【產品範疇】 Mobile/TCON - LCD display driver、OLED display driver Tablet - LCD display driver TV/NB -LCD display driver TCON 產品 【工作內容】 1.DRC/LVS Command file 撰寫&Maintain 2.Laker TF/UDD/PCELL 撰寫 3.PERC rule & 程式的開發 4.Analog design flow development 5.Shell/SKILL/TCL/Python 程式開發 6.新製程廠內的PDK development 7.In house Utility 開發 8.AI 輔助工具的開發與評估

ASIC PD team is hiring both junior and senior engineers, whose work scope is physical design from RTL to GSDII: design quality check, synthesis, formal check, partitioning, constraint (for both design and process), async check, timing analysis/fixing/signoff, also all related flow. Join us, you will work together with expertise in all these areas; you will not only work for physical application, but also drive physical friendly design with all related teams; you will work for the most advanced process/technology, the biggest chip in the world. What you’ll be doing: ．STA for hierarchical design. ．Constraints creation and validation, timing budget. ．Timing closure for hierarchical design. ．Special timing closure, such as io, test, clock etc. ．Async design checks. ．Synthesis, Netlist quality check, Formal Verification. ．Implement chip partition and floorplan. ．Function eco creation ．Develop and enhance entire timing closure flow from frontend (pre-layout) to backend (post-layout) ．Flow automation development, Methodology in any of above areas. What we need to see: ．BSEE, MSEE is preferred ．Project experience in IC design implementation ．Courses taken in circuit design, digital design ．Hand-on experience in EDA software from Synopsys (DC/PT/Formality), Cadence (LEC) is preferred Ways to stand out from the crowd: ．Proficient user of Perl, Python or TCL is preferred ．Excellent English communication skill NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most brilliant and talented people on the planet working for us. If you're creative and autonomous, we want to hear from you!

1.負責部分全定製版圖的設計和驗證。 2.確保IC佈局符合Circuit Designer設計需求及產品、製程、電氣的規範。

analog and digital circuit layout繪製

在Gemini (APU) 晶片系列的設計中,做類比與數位IC佈局(Layout)和DRC, ERC, ANT, LVS之驗證, 該系列的晶片可提供高效率且廣泛的AI應用　　　　　

類比/馬達/電源管理 IC Layout

職務內容： - 隔離型 IC / 傳收 IC 功能測試 - 隔離型 IC / 傳收 IC 測試電路板繪製 - 隔離型 IC / 傳收 IC 功能應用電路設計 歡迎電子、電機相關科系應屆畢業生加入！

【工作內容】 • 我們正在尋找具備先進製程經驗的 IC Layout 工程師，加入團隊後可以參與高階SoC /Analog IP 的實體實現，並負責以下工作： -Mixed-Mode FinFET Layout 設計與繪製，確保電路佈局在效能、面積與可靠性之間取得最佳平衡。 -進行 FinFET 製程相關的 DRC / LVS / ERC 驗證，確保設計符合法規與 Foundry 要求。 -熟悉 XRC & EM/IR 分析流程，進行可靠性評估，並針對潛在問題提出改善方案。 【職務條件】 • 必備條件：具備 FinFET 製程經驗，能獨立進行版圖設計與驗證。 -具備類比電路佈局經驗，了解電路特性與佈局考量，能與設計工程師密切合作。 -具備良好的溝通能力與團隊合作精神，能在專案時程內交付高品質成果。

Main JD: 1. System firmware and diagnostic development for EVT/DVT/PVT (using C/C++)or Automated test program development for EVT/DVT/PVT (using Python) 2. Co-work with cross-functional teams on projects 3. Communicate with customers in English Secondary JD: 1. Assist cross-functional teams on projects to resolve software-related issues 2. Develop some tools to assist EVT/DVT/PVT

IC layout

1) FPGA synthesis, verification, and env. maintain一年以上FPGA使用經驗 2) CP/PT pattern creation and chip validation 3) 熟CMOS原理&CCM設計 4) 懂基礎C/C++,基礎Linux. 5) 編寫技術文件 ,電路設計,IC 訊號測試&功能量測

【產品線描述】 1. LCD應用 Power IC 2. 手機及筆電OLED 應用Power IC 【工作說明】 1. PMIC驗證及規格制定 2. 客戶design-in 工程支援 及 Issue 解析 (需出差) 【必要條件】 碩士以上，電子、電機、控制相關科系畢業，具下列經驗者 1. DC/DC 相關IC驗證經驗尤佳 2. 具基礎電子學/電路學 與 PCB Layout 經驗

1. SOC/IP 整合工作，從RTL到 Netlist 2. clock tree structure design 3. Lint / CDC check / Synthesis/ DFT/ LEC

1.(車規)可靠度測試規劃/執行/資料分析 依據 AEC-Q100 / JEDEC / 客戶規範執行可靠度測試,協助樣品送測、試驗進度追蹤彙報與資料彙整 2.失效原因分析,搜集失效樣品及資料,協同 RD及實驗室，進行失效分析 3.撰寫測試報告，協助完成客戶/內部需求的可靠度文件 4.參與可靠度專案或特定客戶需求