「資深APR工程師」的相似工作

【工作內容】 • 負責車載顯示驅動晶片的物理實現（APR），包括佈局規劃、時鐘樹綜合（CTS）、布線、時序收斂、功耗優化及物理驗證（DRC/LVS）。 • 使用 Synopsys ICC2/Fusion Compiler 進行先進製程節點（如 12nm/7nm）的晶片實現，針對大/中/小尺寸顯示器需求優化 PPA（功耗-效能-面積）。 • 解決車載晶片特有的高可靠性要求（如溫度範圍、EMC/EMI 抗干擾）、低功耗設計（多電壓域）及訊號完整性（SI）問題。 • 與前端設計團隊協作，優化時序約束（SDC），完成 sign-off 時序分析（PrimeTime）。 • 支援 tape-out 流程，生成 GDSII 及交付文件，確保符合車規認證（如 AEC-Q100） 【職務條件】 • 必備工具： -精通 Synopsys ICC2 或 Fusion Compiler 全流程（從 Netlist 到 GDSII）。 -熟悉 PrimeTime（時序簽核）、StarRC（寄生參數提取）、ICV/Calibre（物理驗證）。 【加分項】 • 了解顯示驅動晶片設計（如 TDDI、OLED 驅動）或車載 SoC（如 AutoSAR 架構）。 • 有 ARM Cortex-M/R 或 GPU/Display Pipeline 模組實現經驗。 • 熟悉 UPF/CPF 低功耗流程及車規晶片 DFT（MBIST/Scan）。

【成為円星人】 円星科技由一群專業與充滿熱情的夥伴創立於2011年，為積體電路矽智財設計服務業之新秀，秉持著『成為半導體業最值得信賴之IP公司』的願景，追求永續經營與成長。 誠摯歡迎您成為円星人，加入我們，站上國際舞台！ 一起共同打拚，以精品文化之精神，創造價值，追求卓越！ 【職務簡介】 M31主要業務為向 IC 設計業者和晶圓代工廠授權 IP，此職務為負責支援開發IP的電腦輔助設計CAD職缺。 【將負責的工作內容】 1. PDK QA and maintenance. 2. design porting flow development. 3. EMIR flow development and maintenance. 3. Schematic related tools maintenance and automation programming. 4. IC Layout related tools maintenance and automation programming. 【條件與特質】 1. 擅長工具: - Python - TCL - Virtuoso skill - Experience with Synopsys Custom Compiler is a plus - Experience with Cadence Virtuoso is a plus - Experience with EMIR tool is a plus 2. 有 Analog CAD 相關工作經歷 2 年以上 3. 電機電子/資訊工程相關科系碩士畢業 如果您有以上相關經驗且對此職缺有興趣，歡迎投遞您的履歷！

• Co-work with package design team to complete a substrate layout that will meet the design objectives for performance, cost and quality. • Co-work with SOC team to complete Bump floorplan and RDL routing. • Power mesh/power density flow development and related flow development and enhancement. • Provide power plan result for PR team. • Chip IR signoff : provide the result and solution to APR & package team • Chip level PEM/SEM simulation and fixing plan providing. • SIR/DIR/PEM/SEM result data review and verification. • Familiar with Voltus / Redhawk experience is required.

在Gemini (APU) 晶片系列的設計中,做類比與數位IC佈局(Layout)和DRC, ERC, ANT, LVS之驗證, 該系列的晶片可提供高效率且廣泛的AI應用　　　　　

(1)Analog and Digital IC Layout或具APR經驗者。 (2)熟悉Laker Tool與Calibre verificaiton Tool等工具軟體使用。

• Work on 22nm~6nm design implementation, methodology, and sign-off • Perform floorplan, power plan, place and route, timing closure, ECO • Requirement: - Hands on whole chip APR physical design from netlist to DRC/LVS tapeout - Familiar with Cadence Innovus & Synopsys ICC/ICC2 experience is required

【在華邦，學習不設限，讓AI技術力與你的未來力同步成長!】 我們深信「人才永續」是企業創新的核心動能。華邦持續投資於數據素養與AI應用的培育，支持每一位人才掌握AI與數據應用的核心能力。 ．內部學習平台提供超過4,000堂線上課程，其中包含近850堂資料科學、人工智慧、數據思維與程式技術等多元主題，支援彈性自主學習 ．建立跨部門的 AI實作班與技術社群，定期舉辦研習與交流活動，讓知識轉化為實戰力 ．完善數據應用學習資源，結合資料呈現(Power BI、Tableau)、資料處理(Python、JMP)、流程自動化(Power Automate、UiPath)、AI助手(Copilot)，協助同仁有效以數據驅動決策與創新。 ．搭配專業語言學習平台，提供學習補助與資源，鼓勵同仁持續進修，拓展國際視野 無論你是技術新秀還是資深專才，華邦鼓勵所有領域都能與AI結合，與國際接軌。持續精進、突破自我！ 【邀請您將104履歷同步上傳至華邦官方網站，將使您的履歷優先被主管看見】此職缺履歷登錄網址:https://bit.ly/4eYYFVa [工作內容] 1. Custom Library Management: Creating and maintaining Cadence/ Symbol Lobraries tailored for Flash memory, ensuring accuracy for both CDL and simulation. 2. Design Flow Automation: Driving automation initiatives to streamline and enhance Flash memory design processes. 3. Version Control Administration: Managing our global design platform and version control system for seamless collaboration and data integrity. 4. EDA Environment Optimization: Maintaining and improving our EDA tool integration and performance to provide a robust workspace.

【工作內容】 • 我們正在尋找具備先進製程經驗的 IC Layout 工程師，加入團隊後可以參與高階SoC /Analog IP 的實體實現，並負責以下工作： -Mixed-Mode FinFET Layout 設計與繪製，確保電路佈局在效能、面積與可靠性之間取得最佳平衡。 -進行 FinFET 製程相關的 DRC / LVS / ERC 驗證，確保設計符合法規與 Foundry 要求。 -熟悉 XRC & EM/IR 分析流程，進行可靠性評估，並針對潛在問題提出改善方案。 【職務條件】 • 必備條件：具備 FinFET 製程經驗，能獨立進行版圖設計與驗證。 -具備類比電路佈局經驗，了解電路特性與佈局考量，能與設計工程師密切合作。 -具備良好的溝通能力與團隊合作精神，能在專案時程內交付高品質成果。

1. Knowledgeable in power analysis and IR/EM methodologies, with hands-on experience using Ptpx, Redhawk, or Voltus for power and IREM evaluation. 2. Familiar with the integrated circuit (IC) design flow, capable of performing design, optimization, and verification using tools such as ICC2 or INNOVUS. 3. Experience in developing automation scripts using Python, Perl, TCL, or Shell is a strong plus. 4. Experienced in IO/IP planning, including bump/PAD placement and RDL routing is a plus. 5. Experienced in fundamental circuit structures (e.g., standard cells, IO), with the ability to simulate basic circuits using Hspice or Spectre is a plus.

負責OTP & TEST CHIP 佈局及Merge

1. Physical design and verification 2. Physical integration 3. Fully layout if necessary

1.Designs IC sockets and components using design tool provided. 2.Conduct performance forecast, simulation, and analysis 3.Modifies drawings based on NBOs. 4.Measures locally made parts and customer packages. 5.Measures IC socket and components. 6.Translates engineering documents into English (by special assignment). 7.Verifies customer package drawing to existing socket drawing. 8.Modifies and assembles parts for IC sockets. 9.Act as global engineering members. 10.Provides technical support for Sales, field support as needed. 11.Provides technical support to customers through phone, email, and on-site Work. 12.Interacts with vendors on issues of piece parts manufacturing. 13.Provides quality check for assembly and piece parts. 14.Test new products. 15.Improve design quality and speed.

職務內容： - 隔離型 IC / 傳收 IC 功能測試 - 隔離型 IC / 傳收 IC 測試電路板繪製 - 隔離型 IC / 傳收 IC 功能應用電路設計 歡迎電子、電機相關科系應屆畢業生加入！

負責 3D-IC Interposer 與類比 IP 佈局設計 (Virtuoso / Allegro)，確保電性與實體規格，優化設計流程。 熟悉 Layout tools、Foundry PDK為佳。

1. ARM CPU design physical implementation 2. ARM CPU power and timing sign off 3. Physical design flow enhancement for high-speed CPU

1.Chip level IR drop 分析 2.Chip power estimation/calculation 3.IR drop flow 建構 4.IR drop tool 維護 5.撰寫程式

IC layout

請務必投遞官網(12438): https://careers.synopsys.com/job/hsinchu/applications-engineering-staff-engineer-ic-validator/44408/84710683632 You Are: You are an innovative and resourceful engineer with a deep curiosity for solving complex technical challenges at the intersection of hardware and software. With a strong foundation in Electronic Engineering, Computer Science, or a related field, you are adept at leveraging your programming expertise—whether in Python, Tcl, Perl, or similar languages—to streamline and enhance engineering workflows. Your experience within UNIX/Linux environments equips you to navigate high-performance computing scenarios with ease. You thrive in collaborative, cross-functional teams and are energized by the opportunity to work closely with top-tier foundry partners and leading fabless companies. Your keen understanding of physical verification flows—such as DRC, LVS, PERC, FILL, and DFM—sets you apart, and you are eager to deepen your expertise in SoC physical design enablement, process effect analysis, and signoff. You are detail-oriented, capable of producing clear technical documentation, and communicate with clarity and empathy across diverse audiences. What You’ll Be Doing: 1.Delivering advanced physical verification solutions (DRC/LVS/PERC/Fill) for top-tier foundries and key fabless customers, ensuring high-quality silicon signoff. 2.Developing and validating process design kits (PDKs) and verification methodologies in collaboration with R&D and customer teams. 3.Partnering with R&D to innovate and improve Synopsys tools and flows, contributing to the evolution of physical verification technologies. 4.Providing hands-on customer support, troubleshooting issues, and delivering timely resolutions that enhance customer satisfaction and product adoption. 5.Coordinating with internal teams, including product managers and end-users, to align on best practices and ensure seamless integration of new technologies. 6.Documenting technical solutions, validation methods, and customer workflows for knowledge sharing and process improvement. 7.Staying up to date on industry trends and applying new insights to continuously optimize verification processes and tools. The Impact You Will Have: Accelerate the adoption and success of Synopsys physical verification products in leading-edge semiconductor manufacturing processes. Drive the development of robust PDKs and methodologies that enable customers to achieve first-time-right silicon. Enhance the quality and reliability of Synopsys verification tools through direct feedback and collaborative innovation with R&D teams. Strengthen Synopsys’ reputation as a trusted partner to top-tier foundries and fabless customers worldwide. Facilitate faster product cycles and reduced time-to-market for customers by delivering efficient and effective signoff solutions. What You’ll Need: BS or MS degree in Electronic Engineering, Computer Science, or a related field. Proficiency in at least one programming language, such as Python, Tcl, or Perl. Hands-on experience with UNIX/Linux environments and command-line tools. Familiarity with physical verification flows (DRC, LVS, PERC, FILL, DFM) and understanding of complex layout/electrical design rules. Strong investigative, analytical, and problem-solving abilities, with a passion for learning new technologies. Ability to produce clear, concise technical documentation and validation reports. Prior knowledge of tool/runset development/support and experience with SoC physical design is a plus.

歡迎對象： 1. 擁有電路佈局設計 (IC Layout) 相關經驗一年以上者 2. 對電路佈局設計 (IC Layout) 有興趣者 3. 相關科系，或非本科系都可 職務內容： 1. 熟悉 Layout Edit Tool 的操作 2. 熟悉 Physical Verification Tool 的操作 3. 負責 IC 電路佈局、優化和驗證 4. 確保 IC 佈局符合 Circuit Designer 設計需求及產品、製程等規範

1. Analog mixed signal IC layout 2. 熟悉IC Layout tool