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6 天內聯絡過求職者
徵才積極度:非常活躍
應徵
3 天內聯絡過求職者
徵才積極度:極為活躍
應徵
10/23
Provide design services for our SoC ※ Responsibilities: • Participate in architecture definition and modeling. • Contribute to micro-architecture specification and reviews. • Review industry standard specs and ensure IPs are kept up to date for compliance. • Define design partitioning for efficient IP/sub-system/full chip implementation. • Review and provide feedback on verification plans and methodology. • Drive block/chip/system level development and execution. • Work with Hard IP designers, verification, validation, Firmware engineers and architects to produce thoroughly verified, robust IP. • Actively participate in post-silicon bring-up, validation and compliance testing.
2 天內處理過履歷
徵才積極度:活躍
應徵
9/08
2 天內處理過履歷
應徵
6/05
1 天內處理過履歷
應徵
9/08
3 天內處理過履歷
應徵
9/08
1. ASIC project leader 2. 需與客戶討論 ASIC spec , 管理 project 進度, 定期與客戶開會, 協調內部 RD 資源解決project 從開始到量產的所有問題.
3 天內處理過履歷
徵才積極度:極為活躍
應徵
6/05
1. Business development to explore business opportunities and engage with customers to complete the sales cycle. 2. Responsible for customer strategy, promotion material, and value-selling. 3. Collaboration with 3rd party partner.
應徵
9/03
3 天內處理過履歷
應徵
9/01
1. Participate in digital design specification, architecture definition, and microarchitecture planning. 2. Conduct FPGA prototyping, testing, and debugging of digital IP designs. 3. Collaborate closely with analog/mixed-signal design teams, firmware engineers, and system engineers to ensure successful product integration. 4. Develop, implement, and verify RTL code (Verilog/SystemVerilog) for high-speed Serdes interfaces including USB, DP, HDMI, DDR and PCIe.
6 小時前處理過履歷
徵才積極度:非常活躍
應徵
9/08
3 天內處理過履歷
應徵
8/04
ASIC design verification engineer responsible for the design, verification, and evaluation of digital circuits in high-
4 天內處理過履歷
應徵
7/23
2 天內聯絡過求職者
徵才積極度:非常活躍
應徵
9/01
3 小時前處理過履歷
應徵
8/27
4 天內聯絡過求職者
徵才積極度:非常活躍
應徵
7/21
Marvell products. ASIC design engineer responsible for post-RTL design flow. You will be responsible for block and /or
12 小時前處理過履歷
徵才積極度:非常活躍
應徵
8/11
應徵
儲存清單
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