英屬開曼群島商世芯股份有限公司台灣分公司

1. Proficient in fundamental circuit structures (e.g., standard cells, IO), with the ability to simulate basic circuits using Hspice or Spectre. 2. Experienced in IO/IP planning, including bump/PAD placement and RDL routing. 3. Familiar with the integrated circuit (IC) design flow, capable of performing design, optimization, and verification using tools such as ICC2 or INNOVUS. 4. Knowledgeable in power analysis and IREM methodologies, with hands-on experience using Ptpx, Redhawk, or Voltus for power and IREM evaluation. 5. Experience in developing automation scripts using Python, Perl, TCL, or Shell is a strong plus. 6. Experience in layout design using Virtuoso or Laker is a plus. 7. Knowledge of one or more of the following domains is preferred: semiconductor processes, ESD protection, digital and analog circuit design, signal integrity, power integrity, timing analysis, physical verification, thermal analysis, and mechanical analysis.

1. ICC2, Innvous for IO/IP planning, placement, bump &RDL. 2. Physical verification. Be familiar with package flow is better 3. Knowledge about process, ESD protect principle to do fullchip ESD design. 4. Perform power analysis with PTPX and IR/EM analysis with Redhawk or voltus. 5. Develop Perl/TCL/Shell scripts for flow and procedure automation 6. Work proactively with EDA engineers and tool suppliers to debug tool functionality and bugs. 7. Design optimization of 2.5D/3D advanced silicon/package technology features to enable strong product differentiation. 8. 2.5D/3D -IC Test Chips validation of 2.5D/3D -IC technology platforms and design methodology.

1. Knowledge about process, ESD protect principle to do fullchip ESD design. 2. Familiar with ICC2, Innvous for IO/IP planning, placement, bump &RDL. 3. Familiar with power analysis with PTPX and IR/EM analysis with Redhawk or voltus. 4. Familiar with Perl/TCL/Shell scripts for flow and procedure automation 5. Work proactively with EDA engineers and tool suppliers to debug tool functionality and bugs. 6. Design optimization of 2.5D/3D advanced silicon/package technology features to enable strong product differentiation. 7. 2.5D/3D -IC Test Chips validation of 2.5D/3D -IC technology platforms and design methodology. 8. Lead the team to handle multiple projects simultaneously and ensure both quality and schedule.

1. Design and implementation of DFT circuit, including Scan, mbist, bscan, etc.. 2. DFT implementation of IP, such as USB, MIPI, DDR, PCIE, etc.. 3. Provide correct DFT SDC and guideline; quickly respond to DFT timing/routing encountered by the APR team. 4. Complete DFT verification and independently and quickly solve related simulation verification work. 5. Build the DFT plan of the SOC chip. 6. Cooperate with test engineers to complete DFT testing of chips and conduct fault and yield analysis. 7. Guide Jr. DFT engineers to complete design tasks.

1. Perform gate level netlist to GDS design independently including and not limit to floor planning, place&route, clock tree synthesis, timing sign off and physical verification. 2. For DFT engineers, need to able to implement scan chain, atpg, mbist, jtag, IP test logic into netlist. 3. Perform design IP implementation, IR drop analysis, DFT, STA and foundry merge. 4. Work with manager to achieve assigned tape out target.

1. Responsible for the digital back-end physical implementation from netlist to GDS, completing the chip sign-off process. 2. Complete the full-chip floorplanning, including chip partitioning, power and ground network, placement of critical modules, utilization optimization, pin assignment. 3. Complete the overall digital back-end design of the chip, including placement, clock tree implementation, timing closure, power calculation, IR drop analysis, SI closure, and physical verification. 4. Co-work with front-end design team for the logic, clock and timing optimization. 5. Co-work with package team for the substrate design and SIPI simulations.

1. Responsible for the digital back-end physical implementation from netlist to GDS, completing the chip sign-off process. 2. Complete the full-chip floorplanning, including chip partitioning, power and ground network, placement of critical modules, utilization optimization, pin assignment. 3. Complete the overall digital back-end design of the chip, including placement, clock tree implementation, timing closure, power calculation, IR drop analysis, SI closure, and physical verification. 4. Co-work with front-end design team for the logic, clock and timing optimization. 5. Co-work with package team for the substrate design and SIPI simulations.

Responsible for developing custom IP for SoC design from specification definition, circuit design to testing, and familiar with component and process characteristics.

1. Provide IC package solution supporting pre-sales activity; timely respond package inquiries. 2. Collaborate with subcontractor's engineering team and IC designer to deliver robust package solutions. 3. Participate IC package substrate design, design review; initiate package specs and documentation. 4. Work with DE/SIPI/PM, subcontractor for prototype build, package characterization and simulation.

1. Provide IC package solution supporting pre-sales activity; timely respond package inquiries. 2. Collaborate with subcontractor's engineering team and IC designer to deliver robust package solutions. 3. Participate IC package substrate design, design review; initiate package specs and documentation. 4. Work with DE/SIPI/PM, subcontractor for prototype build, package characterization and simulation.

1. Work with customers and team members to setup test environment to make products delivery smoothly. 2. ES delivery handing 3. Data collection 4. Characterization execution

1. Early discussion for testing solution. 2. Testing SW/HW development. 3. Silicon brings up (debugging / ES delivery / data analysis). 4. Characterization execution.

1. Flip chip package substrate design, and 2.5D experience is a plus. 2. Provide optimization design proposal.  3. Co-work closely with substrate suppliers/SIPI team directly.  4. Design rule maintenance.

Be a chip architecture planner to provide a competitive and valuable solution to sales and customers. This role will consolidate a project scope by achieving technology feasibility and competitiveness study, resource and schedule planning, cost break down for quotation. Responsibility: 1. Pre-sale technical tasks and RFQ follow up. 2. Architecture planner to propose total solution of algorithm, design, IP, P&R, software, process, package, testing, yield and reliability with respect to application scenarios and RFQ. 3. Assessment to the feasibility, competitiveness and risk of proposed total solution. 4. Share solution knowledge base of historical projects within focused fields. 5. Connect and coordinate cross-departments with customers for solution proposal. 6. Project schedule planning and resource evaluation. 7. Cost break down for quotation proposal.

1. Execuse purchasing request/order process. 2. Trade term and price driving/negotiation with assembly / testing supplier. 3. New supplier development and engagement. 4. Business outlook and relationship maintains.

1. PR/PO process. 2. Trade tern and price driving / negotiation with assy / testing supplier. 3. New supplier development and engagement. 4. Business outlook and relationship maintains.

1. Be responsible for setting up and tuning the Linux system corresponding to EDA platform. 2. Be responsible for the daily maintenance of the servers, network equipment and related application components to ensure the reliable operation of the system. 3. Troubleshoot hardware and software errors by running diagnostics, documenting problems and resolutions, prioritizing problems, and assessing impact of issues. 4. Be responsible for collecting data from servers and systems and able to provide various reports based on this data to display operational status.

1. Be responsible for setting up and tuning the Linux system corresponding to EDA platform. 2. Be responsible for the daily maintenance of the servers, network equipment and related application components to ensure the reliable operation of the system. 3. Troubleshoot hardware and software errors by running diagnostics, documenting problems and resolutions, prioritizing problems, and assessing impact of issues. 4. Be responsible for collecting data from servers and systems and able to provide various reports based on this data to display operational status.

1. Assist the executive in managing daily schedules, meeting arrangements, and travel plans. 2. Prepare meeting materials, take meeting minutes, and follow up on action items. 3. Handle confidential documents, draft reports, and prepare presentations, ensuring data integrity and accuracy. 4. Serve as the liaison between the executive and other departments, ensuring smooth information flow and coordinating internal resources to complete projects. 5. Assist the executive with communication needs involving external partners, clients, or industry experts, and help organize meetings and events. 6. Assist in planning, executing, and monitoring key projects, including tracking progress and evaluating outcomes.

1. 總機電話接聽及訪客接待。 2. 文件收發及辦公室環境管理。 3. 一般性庶務盤點、採購及請款工作。 4. 零用金管理。 5. 辦公室大樓及各廠商聯絡窗口。 6. 其他相關行政總務庶務及辦公室服務支援。 7. 其他主管交代事項。 約聘期間: 2025/8/1-2026/7/31