英屬開曼群島商世芯股份有限公司台灣分公司

內湖科

公司介紹

產業類別

聯絡人

Anita

產業描述

半導體相關業

電話

暫不提供

資本額

傳真

暫不提供

員工人數

500人

地址

台北市內湖區文湖街12號9樓 (內湖科技園區)


公司簡介

英屬開曼群島商世芯股份有限公司台灣分公司(世芯-KY:3661),總部設於臺灣臺北,專為高複雜度,高產量SoC設計提供矽設計及量產服務。世芯成立於2003年,由一群來自矽谷及日本的優秀工程師創辦。隨著IC設計技術複雜度的提高和產品快速上市的需求,世芯致力於為客戶提供最高效益/成本比的解決方案,確保客戶一次投片成功並快速將產品導入市場。世芯的目標客戶主要針對成長快速且追求量大市場的IC供應商/系統廠商,這些應用市場包含娛樂裝置、手機,高畫質電視,通訊設備,電腦及其他消費性電子產品的IC。世芯成立以來,已完成眾多高階製程及高複雜度SoC設計的成功案例,並於2014年10月28日掛牌上市。更多關於世芯的介紹請參考公司網站:http://www.alchip.com 台北總公司:台北市內湖區文湖街12號9樓 (02)2799-2318 新竹分公司:新竹縣竹北市台元科技園區台元一街1號11樓之1(03)560-1218

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主要商品 / 服務項目

1. High-end SoC design services 高階特殊應用晶片設計服務 2. ASIC turnkey services 產品工程服務

公司環境照片(2張)

福利制度

法定項目

其他福利

1.分紅奬金 (依公司獲利、組織目標達成率與個人績效決定) 2.三節獎金 3.勞健保及退休金提撥 4.員工團保 (意外、壽險及防癌險) 5.國內外旅遊/旅遊補助 6.工程師介紹獎金 7.全薪病假及彈性休假 8.員工汽機車停車位或交通津貼 9.員工健康檢查 10.福委會相關福利活動

工作機會

工作性質
每頁 20 筆
廠商排序
9/23
台北市內湖區經歷不拘大學待遇面議
1. Knowledgeable in power analysis and IR/EM methodologies, with hands-on experience using Ptpx, Redhawk, or Voltus for power and IREM evaluation. 2. Familiar with the integrated circuit (IC) design flow, capable of performing design, optimization, and verification using tools such as ICC2 or INNOVUS. 3. Experience in developing automation scripts using Python, Perl, TCL, or Shell is a strong plus. 4. Experienced in IO/IP planning, including bump/PAD placement and RDL routing is a plus. 5. Experienced in fundamental circuit structures (e.g., standard cells, IO), with the ability to simulate basic circuits using Hspice or Spectre is a plus.
應徵
9/22
台北市內湖區經歷不拘大學待遇面議
負責 3D-IC Interposer 與類比 IP 佈局設計 (Virtuoso / Allegro),確保電性與實體規格,優化設計流程。 熟悉 Layout tools、Foundry PDK為佳。
應徵
9/23
台北市內湖區經歷不拘大學待遇面議
Analyzing voltage drop across the power grid under different operating conditions. Evaluating current density in metal interconnects and reliability concerns. Design, analyze, and improve power grids. Cross-functional collaboration – working with design, package, and verification teams. Automation and Flow Development – gaining hands-on experience in scripting to improve design efficiency.
應徵
9/18
台北市內湖區5年以上大學以上待遇面議
1. Design and implementation of DFT circuit, including Scan, mbist, bscan, etc.. 2. DFT implementation of IP, such as USB, MIPI, DDR, PCIE, etc.. 3. Provide correct DFT SDC and guideline; quickly respond to DFT timing/routing encountered by the APR team. 4. Complete DFT verification and independently and quickly solve related simulation verification work. 5. Build the DFT plan of the SOC chip. 6. Cooperate with test engineers to complete DFT testing of chips and conduct fault and yield analysis. 7. Guide Jr. DFT engineers to complete design tasks.
應徵
9/11
台北市內湖區1年以上大學待遇面議
1. Perform gate level netlist to GDS design independently including and not limit to floor planning, place&route, clock tree synthesis, timing sign off and physical verification. 2. For DFT engineers, need to able to implement scan chain, atpg, mbist, jtag, IP test logic into netlist. 3. Perform design IP implementation, IR drop analysis, DFT, STA and foundry merge. 4. Work with manager to achieve assigned tape out target.
應徵
9/18
台北市內湖區5年以上大學以上待遇面議
1. Responsible for the digital back-end physical implementation from netlist to GDS, completing the chip sign-off process. 2. Complete the full-chip floorplanning, including chip partitioning, power and ground network, placement of critical modules, utilization optimization, pin assignment. 3. Complete the overall digital back-end design of the chip, including placement, clock tree implementation, timing closure, power calculation, IR drop analysis, SI closure, and physical verification. 4. Co-work with front-end design team for the logic, clock and timing optimization. 5. Co-work with package team for the substrate design and SIPI simulations.
應徵
9/18
台北市內湖區5年以上大學以上待遇面議
1. Responsible for the digital back-end physical implementation from netlist to GDS, completing the chip sign-off process. 2. Complete the full-chip floorplanning, including chip partitioning, power and ground network, placement of critical modules, utilization optimization, pin assignment. 3. Complete the overall digital back-end design of the chip, including placement, clock tree implementation, timing closure, power calculation, IR drop analysis, SI closure, and physical verification. 4. Co-work with front-end design team for the logic, clock and timing optimization. 5. Co-work with package team for the substrate design and SIPI simulations.
應徵
9/18
台北市內湖區經歷不拘碩士以上待遇面議
Responsible for developing custom IP for SoC design from specification definition, circuit design to testing, and familiar with component and process characteristics.
應徵
9/18
新竹縣竹北市5年以上大學以上待遇面議
1. Provide IC package solution supporting pre-sales activity; timely respond package inquiries. 2. Collaborate with subcontractor's engineering team and IC designer to deliver robust package solutions. 3. Participate IC package substrate design, design review; initiate package specs and documentation. 4. Work with DE/SIPI/PM, subcontractor for prototype build, package characterization and simulation.
應徵
9/18
新竹縣竹北市10年以上大學以上待遇面議
1. Provide IC package solution supporting pre-sales activity; timely respond package inquiries. 2. Collaborate with subcontractor's engineering team and IC designer to deliver robust package solutions. 3. Participate IC package substrate design, design review; initiate package specs and documentation. 4. Work with DE/SIPI/PM, subcontractor for prototype build, package characterization and simulation.
應徵
9/18
新竹縣竹北市2年以上大學待遇面議
1. Work with customers and team members to setup test environment to make products delivery smoothly. 2. ES delivery handing 3. Data collection 4. Characterization execution
應徵
9/18
新竹縣竹北市5年以上大學待遇面議
1. Early discussion for testing solution. 2. Testing SW/HW development. 3. Silicon brings up (debugging / ES delivery / data analysis). 4. Characterization execution.
應徵
9/18
新竹縣竹北市5年以上大學以上待遇面議
1. Flip chip package substrate design, and 2.5D experience is a plus. 2. Provide optimization design proposal.  3. Co-work closely with substrate suppliers/SIPI team directly.  4. Design rule maintenance.
應徵
9/18
新竹縣竹北市5年以上大學待遇面議
Be a chip architecture planner to provide a competitive and valuable solution to sales and customers. This role will consolidate a project scope by achieving technology feasibility and competitiveness study, resource and schedule planning, cost break down for quotation. Responsibility: 1. Pre-sale technical tasks and RFQ follow up. 2. Architecture planner to propose total solution of algorithm, design, IP, P&R, software, process, package, testing, yield and reliability with respect to application scenarios and RFQ. 3. Assessment to the feasibility, competitiveness and risk of proposed total solution. 4. Share solution knowledge base of historical projects within focused fields. 5. Connect and coordinate cross-departments with customers for solution proposal. 6. Project schedule planning and resource evaluation. 7. Cost break down for quotation proposal.
應徵
9/18
新竹縣竹北市5年以上大學待遇面議
1. Be responsible for setting up and tuning the Linux system corresponding to EDA platform. 2. Be responsible for the daily maintenance of the servers, network equipment and related application components to ensure the reliable operation of the system. 3. Troubleshoot hardware and software errors by running diagnostics, documenting problems and resolutions, prioritizing problems, and assessing impact of issues. 4. Be responsible for collecting data from servers and systems and able to provide various reports based on this data to display operational status.
應徵
9/18
台北市內湖區5年以上大學待遇面議
1. Be responsible for setting up and tuning the Linux system corresponding to EDA platform. 2. Be responsible for the daily maintenance of the servers, network equipment and related application components to ensure the reliable operation of the system. 3. Troubleshoot hardware and software errors by running diagnostics, documenting problems and resolutions, prioritizing problems, and assessing impact of issues. 4. Be responsible for collecting data from servers and systems and able to provide various reports based on this data to display operational status.
應徵
9/18
新竹縣竹北市經歷不拘高中月薪33,000以上
1. 總機電話接聽及訪客接待。 2. 文件收發及辦公室環境管理。 3. 一般性庶務盤點、採購及請款工作。 4. 零用金管理。 5. 辦公室大樓及各廠商聯絡窗口。 6. 其他相關行政總務庶務及辦公室服務支援。 7. 其他主管交代事項。 約聘期間: 2025/8/1-2026/7/31
應徵
9/18
台北市內湖區2年以上大學以上待遇面議
1. Relay Silicon IP questions to IP vendors from internal teams. 2. Handle Silicon IP license agreement negotiation and internal procedures. 3. Maintain IPS knowledge database.
應徵
9/18
新竹縣竹北市3年以上大學以上待遇面議
1. Convert sales forecast/ demand, develop effective production/ materials planning and scheduling. 2. Issue work order to OSATs, manage WIP, cycle time and hold/ aged materials. 3. Key raw materials inventory management to achieve company's target. 4. NPI schedule management from Fab process to FG delivery. 5. Operation transaction in ERP system.
應徵
9/18
台北市內湖區2年以上大學待遇面議
1. 熟悉生產BOM架構、流程及邏輯,維護成本結轉流程。 2. 審核料件進耗存流程及相關單據。 3. 原物料立帳作業,審核廠商貨款或費用等應付款項帳務。 4. 存貨盤點/報廢作業。 5. 製作成本管理分析報表。 6. 配合會計師查核作業及資料提供。 7. 完成主管交辦事項。
應徵
9/18
台北市內湖區10年以上大學待遇面議
1. Plan and execute internal audit assignments in accordance with the annual audit plan, and issue related reports and improvement recommendations. 2. Conduct self-assessments of internal control systems for all departments and subsidiaries. 3. Evaluate the design and operating effectiveness of the internal control system and optimize internal control procedures. 4. Track the progress of audit findings remediation and regularly report on corrective action status. 5. Perform special audits and investigations on significant irregularities. 6. Submit audit reports to the Audit Committee, Board of Directors. 7. Coordinate and communicate to resolve interdepartmental process issues and drive process improvements. 8. Support legal and regulatory compliance and assist in the development and implementation of audit-related policies. 9. Complete tasks assigned by supervisors.
應徵
9/18
台北市內湖區5年以上專科待遇面議
1. Implementing and maintaining policy/procedures/office administrative systems. 2. Monitor and report on office expenses, supply inventory, and administrative budgets. 3. Supervising, mentoring, training, and coaching office team members and delegating assignments. 4. Coordinating employees' domestic and international travel, including flight, hotel, and car rental reservations. 5. Responsible for company's annual Greenhouse Gas Inventories and audit. 6. Work with employee welfare committee matters such as welfare project planning and execution, budget control, regulation editing, etc. 7. Organizing the company's conferences and events. 8. Organizing maintenance companies to keep the office clean and safe and ensure its appliances are in good working order. 9. Reporting office progress to senior management and working with them to improve office operations and procedures. 10. Other supervisor's assignments.
9/18
台北市內湖區2年以上大學待遇面議
1. Handle Employee stock option plan and stock affairs-related operations. 2. File material information and various announcements on the Market Observation Post System (MOPS). 3. Arrange and assist with shareholders’ meetings and other related meetings and tasks. 4. Assist in the implementation of corporate governance evaluations. 5. Disclose, maintain, and enhance sustainability information. 6. Support departmental operations and handle assignments from supervisors.
應徵
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