鴻軒科技股份有限公司

1. 類比IP相關功能的設計與實現 ADC, DAC, OSC, PLL, high speed interface...etc. 2. 類比IP設計方法和品質改進 3. 類比IP仿真與分析 4. 與第三方類比 IP 供應商合作 5. 與數位電路作co-sim

1. 類比IP相關功能的設計與實現 ADC, DAC, OSC, PLL, high speed interface...etc. 2. 類比IP設計方法和品質改進 3. 類比IP仿真與分析 4. 與第三方類比 IP 供應商合作 5. 與數位電路作co-sim

1.數位IP相關功能的設計與實現 2.數位IP仿真與FPGA驗證 3.數位IP/subsys/chip_top的前段整合流程signoff 4.ISO 26262 FMEDA 設計和品質改進 5.與第三方數位 IP 供應商合作

1.數位IP相關功能的設計與實現 2.數位IP仿真與FPGA驗證 3.數位IP/subsys/chip_top的前段整合流程signoff 4.ISO 26262 FMEDA 設計和品質改進 5.與第三方數位 IP 供應商合作

Join our Automotive SoC design team and drive the development of Design-for-Test (DFT) architecture for next-generation automotive system-on-chips. You will own DFT methodology definition, design, and implementation, collaborating closely with RTL, physical-design, and test-engineering teams to deliver high-quality, ISO 26262-compliant silicon. 1. Define and implement SoC-level DFT architecture (SCAN, MBIST, LBIST, boundary scan, JTAG, etc.). 2. Support the full product life-cycle from new-product introduction (NPI) through mass production (MP): * Develop and debug ATE test programs. * Drive test-coverage closure and yield improvement. * Optimize test time and cost. 3. Interface with IP owners, test engineers, board-design, and process teams to ensure CP/FT/SLT test requirements are met. 4. Provide technical leadership on automotive functional-safety (ISO 26262) DFT flows and documentation.

Join our Automotive SoC design team and drive the development of Design-for-Test (DFT) architecture for next-generation automotive system-on-chips. You will own DFT methodology definition, design, and implementation, collaborating closely with RTL, physical-design, and test-engineering teams to deliver high-quality, ISO 26262-compliant silicon. 1. Define and implement SoC-level DFT architecture (SCAN, MBIST, LBIST, boundary scan, JTAG, etc.). 2. Support the full product life-cycle from new-product introduction (NPI) through mass production (MP): * Develop and debug ATE test programs. * Drive test-coverage closure and yield improvement. * Optimize test time and cost. 3. Interface with IP owners, test engineers, board-design, and process teams to ensure CP/FT/SLT test requirements are met. 4. Provide technical leadership on automotive functional-safety (ISO 26262) DFT flows and documentation.

ASIC Physical / Backend Designer 將負責數位電路的後端實體設計，包括規劃與優化晶片的布局（Floorplan）、電源網格設計（Power Grid Design）、自動布局與繞線（Place and Route）、時脈樹合成（Clock Tree Synthesis）、靜態時序分析（Static Timing Analysis, STA）、物理驗證（Physical Verification）等工作。 主要職責 1. 熟悉以下製程：22nm,16/12nm, 7/5nm Automotive process及其Signoff Criteria. 2. 晶片布局設計：根據Design Specification, Pin Table, Netlist，執行Floorplan規劃及設計。 3. 熟悉Safety Specification Format (SSF)及其實作流程。 4. 時序分析和優化：進行靜態時序分析，熟悉CTS相關技術，確保晶片具備必要的性能，並解決潛在的Timing Violations. 5. 電源架構規劃：熟悉UPF流程，具備Multi-Voltage設計經驗。 6. 功耗分析及優化：熟悉IR分析流程，進行Power Grid優化以符合設計要求。 7. 面積優化：在滿足設計約束條件的前提下，優化晶片布局以達到最小化面積目標。 8. 設計驗證：執行物理驗證(PV)工作，包括DRC（設計規則檢查）、LVS（佈局與網表檢查）等，確保設計符合製造要求。 9. 了解製造相關流程，包括封裝設計和製造約束條件。 10. 與團隊協作：與前/中端設計工程師、製造工程師及測試團隊緊密合作，確保設計符合需求。

ASIC Physical / Backend Designer 將負責數位電路的後端實體設計，包括規劃與優化晶片的布局（Floorplan）、電源網格設計（Power Grid Design）、自動布局與繞線（Place and Route）、時脈樹合成（Clock Tree Synthesis）、靜態時序分析（Static Timing Analysis, STA）、物理驗證（Physical Verification）等工作。 主要職責 1. 熟悉以下製程：22nm,16/12nm, 7/5nm Automotive process及其Signoff Criteria. 2. 晶片布局設計：根據Design Specification, Pin Table, Netlist，執行Floorplan規劃及設計。 3. 熟悉Safety Specification Format (SSF)及其實作流程。 4. 時序分析和優化：進行靜態時序分析，熟悉CTS相關技術，確保晶片具備必要的性能，並解決潛在的Timing Violations. 5. 電源架構規劃：熟悉UPF流程，具備Multi-Voltage設計經驗。 6. 功耗分析及優化：熟悉IR分析流程，進行Power Grid優化以符合設計要求。 7. 面積優化：在滿足設計約束條件的前提下，優化晶片布局以達到最小化面積目標。 8. 設計驗證：執行物理驗證(PV)工作，包括DRC（設計規則檢查）、LVS（佈局與網表檢查）等，確保設計符合製造要求。 9. 了解製造相關流程，包括封裝設計和製造約束條件。 10. 與團隊協作：與前/中端設計工程師、製造工程師及測試團隊緊密合作，確保設計符合需求。

As the Verification Team Lead, you will own the strategy and execution of all verification activities for safety-critical SoC and IP destined for next-generation automotive platforms. You will guide a cross-site team, establish advanced UVM-based methodologies, and partner with design, functional-safety, and product teams to deliver ISO 26262-compliant silicon on schedule. Your leadership will shape verification culture, tooling, and talent development across the organization. 1. Define Verification Strategy - Craft and socialize block-, subsystem-, and full-chip verification plans aligned with functional-safety goals and program milestones. 2. Lead & Mentor - Direct a DV team; recruit, coach, and develop talent to build a high- performance verification organization. 3. Architect Verification Infrastructure - Establish reusable UVM libraries, scoreboards, and functional-safety checkers; champion best-in-class methodologies and tools. 4. Stakeholder Alignment - Interface with architecture, design, safety, firmware, and test-engineering groups to converge on specs, resolve issues, and de-risk schedules. 5. Automate & Accelerate - Scale regression farms, data-mining dashboards, and result visualization to deliver clear, data-driven sign-off criteria. 6. Post-Silicon Support - Guide bring-up, silicon debug, and automotive qualification (AEC-Q100); correlate lab results to simulation/emulation models. 7. Continuous Improvement - Assess emerging EDA technologies, advocate process enhancements, and foster a culture of innovation and ownership.

As the Verification Team Lead, you will own the strategy and execution of all verification activities for safety-critical SoC and IP destined for next-generation automotive platforms. You will guide a cross-site team, establish advanced UVM-based methodologies, and partner with design, functional-safety, and product teams to deliver ISO 26262-compliant silicon on schedule. Your leadership will shape verification culture, tooling, and talent development across the organization. 1. Define Verification Strategy - Craft and socialize block-, subsystem-, and full-chip verification plans aligned with functional-safety goals and program milestones. 2. Lead & Mentor - Direct a DV team; recruit, coach, and develop talent to build a high- performance verification organization. 3. Architect Verification Infrastructure - Establish reusable UVM libraries, scoreboards, and functional-safety checkers; champion best-in-class methodologies and tools. 4. Stakeholder Alignment - Interface with architecture, design, safety, firmware, and test-engineering groups to converge on specs, resolve issues, and de-risk schedules. 5. Automate & Accelerate - Scale regression farms, data-mining dashboards, and result visualization to deliver clear, data-driven sign-off criteria. 6. Post-Silicon Support - Guide bring-up, silicon debug, and automotive qualification (AEC-Q100); correlate lab results to simulation/emulation models. 7. Continuous Improvement - Assess emerging EDA technologies, advocate process enhancements, and foster a culture of innovation and ownership.

Join our verification team to ensure the quality and reliability of SoC-level IP used in next-generation automotive systems. You will develop UVM-based environments, drive functional and safety verification, and collaborate with cross-disciplinary teams to deliver ISO 26262-compliant silicon. 1. Plan & execute verification of automotive-grade IP at block, subsystem, and full-chip levels 2. Develop UVM test environments, scoreboards, and coverage to meet quality and safety goals 3. Create diagnostic and stress tests for pre-silicon and post-silicon validation, ensuring performance and robustness under corner conditions 4. Collaborate with design, DV, and safety teams to define verification strategies, close code/functional coverage. 5. Drive continuous automation of regression, data mining, and result visualization to accelerate tape-out readiness

Join our verification team to ensure the quality and reliability of SoC-level IP used in next-generation automotive systems. You will develop UVM-based environments, drive functional and safety verification, and collaborate with cross-disciplinary teams to deliver ISO 26262-compliant silicon. 1. Plan & execute verification of automotive-grade IP at block, subsystem, and full-chip levels 2. Develop UVM test environments, scoreboards, and coverage to meet quality and safety goals 3. Create diagnostic and stress tests for pre-silicon and post-silicon validation, ensuring performance and robustness under corner conditions 4. Collaborate with design, DV, and safety teams to define verification strategies, close code/functional coverage. 5. Drive continuous automation of regression, data mining, and result visualization to accelerate tape-out readiness

1. 負責IC layout的佈局佈線、優化和驗證。 2. 負責部分full custom analog layout的設計和驗證。 3. 確保IC layout符合circuit designer設計需求及DRC/LVS等tapeout signoff

1. 負責IC layout的佈局佈線、優化和驗證。 2. 負責部分full custom analog layout的設計和驗證。 3. 確保IC layout符合circuit designer設計需求及DRC/LVS等tapeout signoff

1. 研究V2X與人機介面可能面臨之安全攻擊 2. 研究底層實體網路可能面臨之安全攻擊 3. 研究重要資料與軟體/韌體之可能安全漏洞 4. 針對車用所需網路安全提出防護機制 5. 實作關鍵防護機制之軟硬體

Job Summary: This role is responsible for defining the architectural and functional specifications of custom integrated circuits to meet the requirements of specific applications. It collaborates with cross-functional teams to ensure the successful development of ASICs, from concept to production. Responsibilities: 1. Architectural Design: Define the high-level architecture of ASICs, considering the requirements and constraints of the target application. Determine the system's functionality and performance goals 2. Specification Development: Create detailed specifications for ASIC components, including microarchitecture, logic design, memory hierarchy, and interface requirements 3. Feasibility Analysis: Evaluate the feasibility of the proposed architecture by performing modeling, simulations, and trade-off analysis 4. Collaboration: Work closely with cross-functional teams, including ASIC designers, hardware engineers, software engineers, and product managers, to ensure the ASIC meets the application's requirements 5. Design Review: Participate in design reviews and provide input on architectural decisions, trade-offs, and optimizations 6. Performance Optimization: Identify and implement performance enhancements and optimizations to meet the target specifications 7. Risk Assessment: Assess potential risks and challenges in the architecture design and propose mitigation strategies

Job Summary: This role is responsible for defining the architectural and functional specifications of custom integrated circuits to meet the requirements of specific applications. It collaborates with cross-functional teams to ensure the successful development of ASICs, from concept to production. Responsibilities: 1. Architectural Design: Define the high-level architecture of ASICs, considering the requirements and constraints of the target application. Determine the system's functionality and performance goals 2. Specification Development: Create detailed specifications for ASIC components, including microarchitecture, logic design, memory hierarchy, and interface requirements 3. Feasibility Analysis: Evaluate the feasibility of the proposed architecture by performing modeling, simulations, and trade-off analysis 4. Collaboration: Work closely with cross-functional teams, including ASIC designers, hardware engineers, software engineers, and product managers, to ensure the ASIC meets the application's requirements 5. Design Review: Participate in design reviews and provide input on architectural decisions, trade-offs, and optimizations 6. Performance Optimization: Identify and implement performance enhancements and optimizations to meet the target specifications 7. Risk Assessment: Assess potential risks and challenges in the architecture design and propose mitigation strategies

Job Summary: This role is in charge of designing the high-level architecture of SoC software, ensuring the scenarios, requirements, and constraints are fulfilled by the combination of hardware and software architecture, and ensuring the feasibility and competitiveness of final products. Responsibilities: 1. Competitor Analysis, IP evaluation, Scenario analysis, and Requirement evaluation 2. Design system architecture and propose HW/SW partition. 3. Evaluate, identify and develop software architecture and solutions. 4. Design software control flow and data flow of hardware IP and ASIC. 5. Evaluation low power, performance, latency, computing power, bandwidth, and throughput and propose optimized solutions. 6. Monitor pre-silicon and post-silicon development to ensure the consistency of function, power, performance, and stability of products.

Job Summary: This role is in charge of designing the high-level architecture of SoC software, ensuring the scenarios, requirements, and constraints are fulfilled by the combination of hardware and software architecture, and ensuring the feasibility and competitiveness of final products. Responsibilities: 1. Competitor Analysis, IP evaluation, Scenario analysis, and Requirement evaluation 2. Design system architecture and propose HW/SW partition. 3. Evaluate, identify and develop software architecture and solutions. 4. Design software control flow and data flow of hardware IP and ASIC. 5. Evaluation low power, performance, latency, computing power, bandwidth, and throughput and propose optimized solutions. 6. Monitor pre-silicon and post-silicon development to ensure the consistency of function, power, performance, and stability of products.

Job Summary: This role is responsible for defining and designing the high-level architecture of complex systems, ensuring that all components, hardware, and software work harmoniously to achieve specific goals and requirements. It collaborates with cross-functional teams to provide architectural guidance throughout the system development lifecycle. Responsibilities: 1. Architectural Design: Define the high-level architecture of complex systems, considering the system's requirements, performance objectives, scalability, and flexibility 2. Requirements Analysis: Collaborate with stakeholders to gather and analyze system requirements, ensuring that architectural decisions align with business and technical goals 3. Component Integration: Ensure that various hardware and software components are integrated effectively within the system architecture, promoting interoperability and reliability 4. Technology Selection: Evaluate and select appropriate technologies, frameworks, and platforms for implementing system components, considering factors such as cost, performance, and scalability 5. System Modeling: Create system models and diagrams to visualize and communicate architectural concepts and designs to cross-functional teams and stakeholders 6. Performance Optimization: Identify and address performance bottlenecks and make recommendations for system-level optimizations