愛爾蘭商益華科技股份有限公司台灣分公司

Essential: The position requires MSEE, or equivalent, with significant and deep industry experience in designing complex protocols and/or hardware systems. MUST have excellent communication skills with both written and spoken English. Fluent and extensive RTL design knowledge using Verilog/SystemVerilog is required along with experience using RTL verification tools and flows. Must excel in and demonstrate solid debugging experience/skills. Emotionally intelligent collaborator and communicator. Experience with team-wide collaboration tools and processes. Drive and ability to schedule workload and plan own tasks effectively as well as coordinate with and adapt to other's needs and priorities when needful. Agile! Adaptive! Strongly recommended: Verification experience using Cadence simulation and/or emulation products is highly desired. Programming experience with scripting languages like Perl, TCL, C-shell is strongly recommended. Experience in memory sub-system design and operation is strongly recommended.

Job Description: This position is in Cadence Pegasus Physical Verification R&D team in Hsinchu, Taiwan. The candidate for this position will be developing design rule check (DRC) and FILL decks for advanced nodes of semiconductor manufacturing, The job involves creating quality check (QC) patterns, writing physical verification DRC and FILL rules and developing decks consisting of these rules. It also involves testing these decks on real customer designs and troubleshooting the deck and tool issues, providing feedback to Pegasus Foundry Team, Pegasus R&D, and foundry partners. Requirement: At least 2 years of previous experience with DRC or FILL deck development, and BS or MS degree in engineering.

This position is for an R&D engineer, who will be involved in developing Innovus Implementation System. The position involves interaction and collaboration with a highly motivated global R&D team. Essential Job Functions: The candidate will be responsible for designing, developing, troubleshooting and debugging software programs in the areas of P&R. Work closely with product engineers/technical sales to provide engineering solutions and workarounds to make customers successful Minimum Qualifications: Highly technical engineer with excellent problem solving skills C/C++ software development experience in Linux environment Strong understanding and extensive usage of data structures and algorithms Great communication skills and a strong desire for working with customers MS in Computer Science or Electrical Engineering. Preferred: Knowledge of physical design algorithms,. Prior R&D experience working on IC physical designs tools Hands on experience using the above physical design tools and knowledge of physical design flows a plus. Experience with Tcl and other scripting languages

Job Description: • Lead the team of software developers to deliver best-in-class tools for design automation • Design and develop advanced automated design flows for 3D-IC and IC Packaging applications • Design and develop cutting-edge automated full design flow place and route solutions, focusing on the advanced manufacturing technologies and solution automation • Apply excellent knowledge of object-oriented paradigm, data structures and algorithms, as well as good communication skills and a problem-solving mindset to deliver new breakthrough automated design technologies • Provide technical leadership on project areas, including software engineering practices • Collaborate on key architecture and design decisions • Contribute to software system design to appropriately incorporate machine learning elements into product features • Plan, design, develop, test and maintain key software enhancements, take responsibility for quality and customer delight in the capabilities implemented by you and the team • Coordinate with other R&D teams, cross-functional teams and customers to keep development and product plans on track • Troubleshoot and resolve system problems and customer issues Responsibilities: • Degree in Electrical or Computer Engineering or equivalent with 12+ years of relevant software development experience. • Proven success in development and productization software products • Strong C/C++ development skills with a good understanding of object-oriented design. • Strong background of computer science fundamentals (data structures, algorithms). • Passionate to learn and explore new technologies and demonstrates good analysis and problem-solving skills. • Experience in EDA tool development preferred. • Experience collaborating with other functions at local or international sites. • Energetic. Self-driven. Good communication, organization, analytical, presentation and people skills. Following experiences will be a plus: • Hands-on technical management. • Proven leadership capabilities. Ability to delegate and empower the team.

Job Description: The Cadence Palladium Platform is world most scalable emulation system that verifies most of the latest design innovations in consumer, mobile and enterprise electronics worldwide. We are looking for talented software engineers to join our team and contribute to the world’s fastest emulator compiler development. You'll have a great opportunity to make a difference by applying your creativity and problem-solving skills, learn and/or apply multi-threading/distributed computing to solve large scale compile problems such logic optimization. Strong understanding of software data structure and algorithms and proficiency in C/C++ are basic job requirements. The job is located in Hsinchu Taiwan. Requirements: - Ph.D or experienced Masters in computer science, computer engineering or related field. - Industry experience in software development or major personal projects or academic work - Strong CS fundamentals background in data structures, algorithms, systems architecture and/or databases - Expert in Tcl, C++, gdb debugging, and general software development skills - Strong desire and ability to work in a fast-paced startup environment - Eagerness to learn and master new technologies and build the best systems possible. Nice to have: -Scripting language skills in one of: Lisp/Skill, Python. -Familiarity with Linux/Unix development. -Exposure to build and version-control systems. -Coursework in Hardware Descript Language, such as Verilog, SystemVerilog, VHD course. -Knowledge of Logic Simulators and exposure to multi-threaded / concurrent programming. -Experience in logic optimization, compilation of RTL memory models, Arithmetic Operators, optimizing the mapped elements, FPGA mappings. CY

At cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. You’ll develop state-of-the-art library characterization tools for our worldwide customers in an exciting and innovative environment. Position Responsibilities:  Full time in industry leading software development  Involvement in local customer engagements in cooperation with global teams  Develop new product features, including invention, design and implementation new algorithms to build industry leading products Desired Qualifications:  Experiences in EDA/IC industry  Experiences in library characterization, spice simulation, or transistor level timing  Effective communication skills, passion to drive a project and to win customers Additional Job Description  Experience in developing library characterization or circuit simulation software  High level understanding of SPICE simulation transistor models  Experience with distributed programming, database design, and cloud APIs for distributed computing  Proficiency designing data structures, algorithms, and software engineering principles  Experience in developing Machine Learning technology and deploy it at customers

Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. [Job Overview] Software Engineer needed for development and support of tools for next generation physical verification tools and products. [Job Responsibilities] The Physical Verification R&D Software Engineering role is a multi-faceted position encapsulating a mix of physical verification software development, algorithm development, software debugging, performance optimization and accuracy analysis. As an R&D engineer, you'll.. - Collaborate with a large team of EDA professionals across multiple cultures to create and deliver best in class next generation software for physical IC application. - Work on complex applications which interface with other applications in a large suite of highly connected applications to enable next-generation physical verification solutions with superior performance and usability. - Write specifications and develop code that satisfies the requirements of our external customers. - Continuously deploy mastery of physical verification applications, as well as physical implementation methodologies, to guide the accuracy, performance and functionality enhancements within the Cadence physical verification suite of products. [Job Qualifications] Desired Skills and Experience (with different levels of experience): - 3+ years of experience in software development using C/C++, with a focus in working with complex algorithms and performance - 1+ years of experience using Linux - Must be a fast learner and must demonstrate strong aptitude for out-of-the-box thinking and problem solving - Algorithmic knowledge relating to graphs is a plus - Experience in deck development for in physical verification is a plus - Experience in physical signoff methodologies within the Physical implementation environment would be an added advantage. Additional Skills/Preferences: Preferred skills include: experience with physical verification, schematic and layout design, SQL, Python.

Prospects to be responsible for Cadence Quantus QRC extraction product and familiar with flow integration with RC extraction. Smartly working with foundry to capture and develop requirement spec for Quantus R&D to develop tool enhancements. Individually working with R&D to qualify Quantus and getting it certified by foundry and released to mutual customers. Position Requirements • MS in EE or CE major is preferred • Experience in RC extraction, LVS, EMIR, simulation or related application, and familiar with Cadence tools such as Quantus, Pegasus, Tempus, Voltus/Voltus-Fi, and Virtuoso is preferred. • Experience in electromagnetic field solver for RC extraction is the plus. • Exerience on circuit design, LVS, RC extraction, simulation, foundry process technology and structure of device element. • Skilled with perl/tcl or other scripting languages on Linux platform for automation is required. • Self-motivated and strong problem solving skill to face the challenges. Leadership experience is the plus.

Job description: Validate HDL debug tools, test automatically script handling and help customers to clarify issues, even find workaround solutions. Requirement: 1. MS degree or above with EE or CS background 2. Understand Verilog/VHDL or has 2+ years-experience in HDL design. 3. The experience of HDL simulator/debug tool verification is plus. 4. Familiar with Linux environment or scripts.

You will work in a team of physical verification experts and will contribute to performance improvements and scalability of an industry-leading software product. You will learn the details of a large project development process in a dynamic corporate environment. Position Requirements: • MS degree in CS/EE or an equivalent with 5+ years of work experience • Quick learning and good communication abilities • Ability to work on a project and do research independently • Excellent programming skills and practical C++ experience • Knowledge of graph algorithms and computational geometry • Python familiarity and EDA domain knowledge are a plus

Objectives of this Role • · Lead the Taiwan field marketing team in delivery of integrated and effective marketing programs and achieve corporate marketing objectives. • · Lead the planning and execution of media relations and social media management. • · Collaborate with corporate marketing, sales, product teams, and external partners to ensure consistent messaging. Responsibilities • 1. Events Management: 1) Plan, organize, and execute marketing activities that drive brand awareness and demand generation in all kinds of events, including large-scale conferences, seminars, workshops, and product campaigns. 2) Lead and define event strategy, event theme, logistics, vendor management, on-site operations, and post-event reporting. • 2. Media Relations, Social Media Management and Public Communications: 1) Develop and execute media outreach strategies to increase overall brand awareness and thought leadership. 2) Coordinate with corporate PR team and internal stakeholders on speaking opportunities and media marketing assets, including press releases, PR translations, blogs, contributed articles, interviews, newsletter, advertisement, etc. 3) Develop and execute localized social media strategies to promote brand visibility, product launch, and event campaigns. 4) Build and maintain relationships with key media, government stakeholders and industry alliances. 5) CSR/ESG branding management and activities to support Corp and local ESG branding visibility. • 3. Cross team collaboration and reporting: 1) Work closely with field sales, regional business and engineering leaders, and corporate teams to align marketing plans, activities, and marketing assets support. 2) Support logistics and purchasing processes for marketing campaigns if needed. Skills and Qualifications • · Bachelor’s degree in Marketing, Communications, Business or related field. • · Above 8 years’ experience in the field of marketing, events management, or media relations, preferably in the technology and semiconductor industry. • · Able to work independently and hands-on logistics support on campaigns and promotions. • · Excellent communication, writing, presentation, interpersonal and project management skills. • · Fluent in English.

Position Description: 1. To provide key technical support in digital IC design implementation product demonstration, and sales presentations. 2. To demonstrate strong ability and to be hands-on in full APR flow including floorplan, placement, timing analysis, CTS, signoff timing closure methodology. 3. To support key customer engagements on the business increase. 4. Have real design tape-out experience especially for advanced node design. 5. To play a leading role among other team members, while receive little instruction on routine and general assignments. Position Requirements: • Master with 10 years working experience or Bachelor with 12+ years’ experience in IC design. (Cadence Innovus experience will be a plus) • Understanding of full APR flow including timing, congestion analysis and low-power methodology. (Experience for Static Timing Analysis, including SI will be plus) • Good communication in English and Chinese, good confidence and good self-motivation. • Be familiar with shell/perl/tcl etc. script language.

Job Description We are seeking a talented individual who will participate Virtuoso PDK (Process Design Kit ) development, quality and PDK applications related projects with leading foundry. This position will support Virtuoso PDK quality delivery, SKILL programming in task delivery, also provide PDK applications related support and interact with customers to overcome challenge in a fact-pace environment. Position Requirements: • MS degree in Electrical Engineering, Computer Engineering or similar areas. • Experience in analog design flow support or PDK delivery. • Knowledge and experience with analog design layout/simulation/digital/analog IC design flow, with layout domain knowledge would be a plus. • Experience in Linux shell environment and script programming, such as Perl and Tcl preferred. • Good communication skills in English. • Desire to learn, to take the challenge and to be a team player.

Position Description: 1. To provide key technical support in digital IC design implementation, product demonstration, and sales presentations. 2. To demonstrate strong ability and to be hands-on in RTL-to-GDSII design methodology, including both challenging low power and high-performance designs. 3. Have real design experience including floorplan and partition, place, CTS, route, STA timing closure, Physical verification, RC extraction, Power Network analysis. 4. Assist in technical evaluation, assessment and delivery of concurrent ASIC/SoC designs. 5. To play a leading role among other team members, while receive little instruction on routine and general assignments. Position Requirements: 1. A bachelor's degree is essential and 3+ years’ experience in IC design, electronic engineering or computer science applications. 2. Ability to understand and articulate technical issues, (and knowledge of) design products and their applications. 3. Requires working knowledge of one or more programming languages, and effective communication and soft skills. 4. An MS degree and/or working experience in multi-nation IC design house/or familiar with EDI/Innovus product is a plus. 5. Good communication in English and good work attitude. 6. Be familiar with shell/Perl/Tcl etc. script language.

Position Description • Develop PEGASUS/PVS DRC, FILL, LVS, LPE rule decks and RCX flow for worldwide foundries. • Manage onsite technical qualification to ensure both PEGASUS/PVS decks and tools are officially qualified by foundries. • Collaborate closely with early adoption customers to track and resolve product issues • Establish communication channels with R&D to capture customer needs and requirement spec. • Work with R&D to enhance and improve PEGASUS/PVS, positioning it as a leading edge Physical Verification tool Position Requirements • B.S. in Electrical Engineering (EE), Computer Science (CS), or related area (or equivalent) and 3 - 5 years of experience with Physical Verification tool support/development OR • M.S. in EE or CS, or related area (or equivalent) and 1 - 3 years of experience with Physical Verification tool support/development • Profound knowledge with Foundry Design Rules and semiconductor fabrication process • Ability to develop PEGASUS/PVS rule deck for worldwide foundries, ensuring quality, performance, and compliance with schedules and qualification requirements. • Proficiency in TCL and PERL scripting is required • Strong English communication skills. • Software development experience preferred; familiarity with Cadence SKILL programming is a plus. • Experience with IC design and CAD support is advantageous.

Position Description: 1. To provide key technical support in digital IC design signoff product (Tempus/TempusECO/Certus) and design closure methodology demonstration, and sales presentations. 2. To demonstrate strong ability and to be hands-on with signoff timing closure flow. 3. To support key customer engagements on the business increase. 4. Have real design tape-out experience especially for advanced node design. Position Requirements: • Master with 3 years working experience or Bachelor with 5+ years’s experience in IC design. (Cadence Tempus experience will be a plus) • Understanding of signoff timing closure flow including STA/SOCV and timing/Power ECO methodology. (Experience for Tempus/Innovus will be plus) • Good communication in English and Chinese, good confidence and good self-motivation. • Be familiar with shell/perl/tcl etc. script language.

主要設備維護事項 1. 辦公室機電、空調、消防等設備巡檢、維護，系統規劃、發包與驗收。 2. 機房設備不斷電系統維護及緊急電源供應，相關故障排除，緊急處理。 辦公室維護事項 1. 辦公環境美化、營繕工程規劃、水電維修、郵務業務，並負責對外聯繫。 2. 維修保養請款申請與核銷、預算執行及費用管控。 3. 採購及維護事務機器以有效管理需求。 4. 配合執行辦公室之租賃與買賣事務之辦理。 5. 管理相關文件檔案（如：合約、會議記錄、書目資料、活動文件）和資料庫系統。 其它 1. 擔任防火管理人。 2. 其它主管交辦事項。 Equipment Maintenance 1. Office equipment maintenance, repair work, system planning, contracting and acceptance for items including electricity, air conditioning, fire protection. 2. Operation and maintenance of equipment in IT room, operation and maintenance of uninterruptible power system and emergency power supply, equipment troubleshooting, and emergency treatment. Office Maintenance 1. Office landscaping, construction work planning, water and electricity maintenance, postal services, and responsible for external contacts. 2. Repair and maintenance requisition application and reimbursement, budget enforcement and expense control. 3. Purchase and maintain business machines, office supplies, general services, and household appliances for effective demand management. 4. Handle the rental and transaction of the office and provide space that meets the needs of the company’s operations. 5. Maintain, update, and manage various document files (such as: contracts, meeting minutes, bibliographic information, and activity documents) and database systems. Others 1. Act as fire management personnel. 2. Other matters assigned by supervisors.

Job Overview: The role is to facilitate faster TAT for customer's cell level certification. As part of the modelling team, you will work on modelling enhancement for advanced process nodes. Work in a tight small group, growth opportunity for people with strong initiative. Job Responsibilities: - With support and help from Cadence Quantus team, you will gradually take full responsibility of customer's certification items. - You will collaborate and coordinate on modelling and engine enhancement to achieve certification goal. - You will also require cross-team collaboration, with Foundry Team, Techgen and xtor level modelling team. Job Qualifications: - Master in EE/CS/Physics/Math desired combined with 2 years of relevant experience , BS in similar area with 4 years of experience - Strong PhD with relevant research background can be considered. - Fluent in C++ coding and basic scripting - Good communication skills, independent, analytical skill, problem solver, team player Additional Skills/Preferences: Capacitance extraction, device modelling, interconnect modelling, electromagnetic simulation, static timing analysis, or place and routing experience welcomed.

Job Overview: The role will grow to be our expert of 3DIC extraction in cell level. You will work with foundries/customers to understand the requirement, work closely with Infrastructure team on a solution architecture. As part of the modelling team, this person will work on modelling/engine enhancement required. Work in a tight small group, growth opportunity for people with strong initiative. Job Responsibilities: - With support and help from the Quantus team, you will gradually take full responsibility of 3DIC extraction engine for cell level. - You will be responsible for infrastructural design and implementation for layer mapping involving both front side and back side, as well as device layers. - You will manage architectural design and data structure implementation in C++ along with modelling teammates. -You will collaborate and coordinate on modelling and engine enhancement required for 3DIC. - You will also require cross-team collaboration, with Foundry Team, Techgen and infrastructure team. Job Qualifications: - Master in EE/CS/Physics/Math desired combined with 2 years of relevant experience , BS in similar area with 4 years of experience +Strong PhD with relevant research background can be considered. -Strong skills in C++ coding, data structures and algorithm, and basic scripting -Good communication skills, independent, analytical skill, problem solver, team player Additional Skills/Preferences: Capacitance, evice modelling, interconnect modelling, electromagnetic simulation, static timing analysis, or place and routing experience welcomed.

Position Description: • Plan and develop strategy to test SPICE/Fast-SPICE simulator. • Support project from foundry and customer. • Develop procedures, test cases, and designs to test, troubleshoot, and debug to make sure the products are performing up to the specifications and upholding software quality standards. • Work closely with a group of professionals to enhance product quality. • Build tools to assist and automate testing using scripting languages. Position Requirements: - MS in Microelectronics, EE, or relevant. - Understanding of semiconductor concepts and Custom IC design. - Exposure to Cadence Virtuoso Design Environment and/or analog circuit simulation is a plus. - Experience in scripting language like Python, Perl, or CSH is a plus - Teamwork and good communication skills.