We are looking for a proactive and challenge-driven engineer to join our memory design team. This role primarily focuses on gate-level simulation and functional verification to ensure product quality and alignment with specifications. 【Key Responsibilities】 1. Memory circuit design and verification. 2. Gate-level verilog simulation against to the datasheet. 3. Failure mode analysis. 【Qualifications】 1. Experience in SRAM, DRAM, or other memory product design. 2. Solid understanding of digital circuit design and Verilog HDL. 3. Experience with simulation and debugging, able to work independently. 4. Hands-on experience in failure mode analysis is a plus. 5. Deep RTL design experience is not required, but strong gate-level simulation and verification skills are essential.
待遇面議
(經常性薪資達 4 萬元或以上)
Prefer Qualifications: 1. Knowledge with standard verification tools and methodologies (SystemVerilog, Verilog, Makefiles, Scripting languages, C+ etc.) 2. Gate-level circuit simulation and understanding 3. Knowledgeable in DDR is a plus
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