TSMC Project | 佈局工程師 Memory Layout Engineer (Ottawa, Canada)

A. Min. qualifications: 1. B.S. in Electrical Engineering, Computer Engineering, or a related field 2. 5-8 yrs of exp. in advanced Memory Layout design, with total 6+ yrs of working exp. 3. In-depth knowledge of Memory compiler architectures, sub-blocks, and functionalities 4. Proven expertise w/ Memory Layout tools like Cadence Virtuoso, Calibre, and Assura 5. Extensive exp. w/ Low-power, High-performance, and High-density memory design across various leading technology nodes (e.g. 3nm, 5nm, 7nm FinFET) 6. Solid understanding of Design for Manufacturability (DFM) and Design for Yield (DFY) principles 7. Strong leadership, communication, and teamwork skills 8. Ability to manage multiple projects and meet deadlines effectively B. Preferred qualifications: 9. Exp. w/ Emerging Memory technologies (e.g., MRAM, ReRAM) 10. Exp. w/ advanced place and route techniques for Memory Layouts 11. Exp. w/ Memory Verification Methodologies and Automation tools 12. Scripting proficiency for Layout Automation and Data Analysis Others: 1. Ability to communicate w/ cross-functional teams in English & Chinese fluently. English reading/speaking is a MUST. 2. Bilingual capability is required (Mandarin & English). 3. Must demonstrate initiative and ownership of assigned responsibilities 4. Ability to work collaboratively and openly with cross-functional Team Leaders, members and client 5. Soft Skills: Good listener, positive attitude, sense of humor, open minded, respect, patience, resolving issues, etc. 6. Exp. working in a collaborative environment and promoting a teamwork mentality 7. Patience to detail, Good analytical thinking and problem-solving skills 8. Ability to predict challenges and seek to proactively head-off obstacles 9. Can work independently (e.g. manage tasks to complete on time, etc.) 10. Can work under pressure 11. Can adapt to fast-paced environment 應徵需附上英文履歷 可以接受英文線上面試 年薪可談