【新創】Senior Design Verification Engineer/Technical Manager _ Hsinchu

We are seeking an experienced Design Verification Engineer with 5+ years of experience to join our dynamic startup team. The ideal candidate will focus on verification of advanced SoC and IP designs, contributing directly to the quality, efficiency, and reliability of our products. Responsibilities: - Lead design verification efforts for high-performance digital/analog IPs and SoCs, including PCIe, CXL, DDR, AXI, AMBA, and Ethernet interfaces. - Develop and maintain verification environments using UVM/SystemVerilog and other verification methodologies. - Drive coverage closure and optimize verification efficiency (e.g., reducing CPU runtime and improving simulation throughput). - Mentor junior engineers and support knowledge sharing within the team. - Collaborate closely with design engineers to identify potential issues early and ensure timely delivery of verified designs. - Document verification plans, strategies, and results clearly for both internal teams and external stakeholders. Qualifications: - 5+ years of experience in Design Verification with a strong track record in complex digital/SoC verification. - Hands-on experience with PCIe, CXL, DDR, AXI, AMBA, Ethernet or similar IPs. - Proficiency in UVM, SystemVerilog, and verification methodologies. - Strong problem-solving skills, attention to detail, and ability to work in a fast-paced startup environment. - Experience mentoring junior engineers and driving cross-functional collaboration. - Previous experience with Synopsys, Realtek, Horizon, or Silicon Motion IPs is a plus.