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「5G手機,AR,VR 顯示技術 數位IC設計工程師(M1)」的相似工作

聯詠科技股份有限公司
共501筆
精選
新竹縣寶山鄉1年以上大學
1. RTL Frontend design flow development and tools support 2. Timing / Power flow 3. DFT flow
應徵
09/11
新竹市2年以上碩士以上
1. Architecture design and RTL implementation of Automotive/Smartphone chipset 2. SoC system power and performance analysis 3. SoC system bus and memory subsystem design, integration, and modeling 4. SoC low power design, integration, and modeling 5. SoC functional safety analysis, design, integration, and modeling 6. SoC cyber security analysis, design, integration, and modeling
應徵
09/09
新竹市經歷不拘碩士以上
【產品線描述】 Evolution Video Display 新興顯示器開發: 1. Gaming monitor controller for LCD, OLED and Mini-LED. 專業電競螢幕,極致沉浸競界曲面螢幕,遊戲體驗身歷其境 2. Public display controller for LCD and Micro/Mini-LED. 大型商用顯示器,極窄邊框拼接電視牆,電子白板 3. Electronic Vehicle Display Controller. AR/2D HUD(抬頭顯示器),車用高速顯示介面 4. Advanced Projector Controller. 低延遲的遊戲投影機、短焦投影機、浮空影像顯示器 【工作說明】 電路硬體設計與開發 1. 顯示器或車用顯示系統架構開發 (System Architecture Development) (a) CPU/MCU架構整合 (b) SoC system bus 與 bridge架構規劃設計 Familiar with AXI/AHB/APB/Arbiter (c) DDR memory controller 2. 高速數位介面 High-Speed I/F (a) HDMI TX/RX link layer (HDMI1.4/2.0/2.1) (b) DP TX/RX link layer (DP1.4/2.0) (c) MIPI RX link layer (d) Vx1 link layer (e) USB Type-C controller 3. Picture Quality(PQ) (a) 視訊影像處理,色彩轉換演算法開發有興趣或具經驗 (b) HDR10+, Dobly Vision 4. FPGA 平台設計 5. APR flow (a) Synthesis/STA (b) DFT (c) Low-power flow (d) APR co-work 【必要條件】(熟悉或有相關經驗) 1. 顯示器或車用顯示 CPU/MCU/DDR controller/bus bridge相關經驗 2. 高速數位介面 High-Speed I/F HDMI TX/RX / DP TX/RX / Vx1 相關經驗 3. Picture Quality(PQ) 視訊影像處理經驗 車用相關IC 設計經驗 4. SOC 整合經驗
09/09
新竹市經歷不拘大學以上
【本職缺優先審核至高通官網投遞人選】請至高通官網上傳英文履歷表https://careers.qualcomm.com/careers/job/446706469791 【Talents who apply job through Qualcomm Career Website will be reviewed and considered as top priority】 https://careers.qualcomm.com/careers/job/446706469791 【The Potential Areas To Work】 The main responsibility of this position is to do the performance verification for world-class custom CPU for mobile and portable computers. 【Roles and Responsibilities】 -Proficiency in one or more areas of CPU architecture: fetch, decode, branch prediction, renaming, execute units, SIMD, load/store, MMU, caches, retire, etc. -Verify performance feature between RTL and model, and have ability to troubleshooting -Work with design team and performance team to develop test case and validate new feature
應徵
09/09
新竹縣竹北市經歷不拘碩士以上
【工作內容】 1. 手機/平板/穿戴/VR/AR…等移動式產品應用環境開發 (軟體/韌體/硬體/FPGA數位電路設計) 2. IC效能最佳化調試演算法研發與自動調校系統開發 3. 協助客戶量產測試方法制定與自動測試系統軟韌體整合 4. 協助客戶產品軟體與驅動程式偵錯 【必要條件】 需熟練C++ / C# 程式語言與Microsoft Visual Studio 開發環境
應徵
09/09
創未來科技股份有限公司消費性電子產品製造業
新竹市經歷不拘碩士以上
## 職務說明 - 應用於無人機雷達系統 - 數位IP架構設計與實作。 - 透過MATLAB/C++協助數位IP驗證 - 透過FPGA整合與驗證。 ## 技能要求 - 具備數位訊號處理經驗 - 具備數位電路設計經驗 - 程式語言必要:Verilog/VHDL, TCL, ##加分條件: - 具備雷達/通訊訊號處理、數位設計架構 - 具備RF/Analog 知識與RF/Analog校準設計 - 程式語言: MATLAB, python, c, c++, Chisel3
應徵
09/12
台北市內湖區3年以上大學
我們專注於3D影像立體雙目視覺技術 產品應用於3D 影像辨識、360 度環景拍照、攝影或AR 與VR 職務內容: ★ USB2.0/3.1或 MIPI 介面之2D/ 3D 影像處理與壓縮之 IC 開發 ★ 影像處理與壓縮相關數位 IP暨產品之開發設計、測試、驗證 條件要求: 1. 對IP Verification, System Verification 有興趣 2. 熟Verilog coding 與 ASIC design Flow 與 Timing Closure 3. 或有 SoC IC 開發經驗 4. 對開發人工智慧((AI) 晶片與邊緣運算有興趣者
應徵
09/11
新竹縣竹北市經歷不拘碩士以上
【產品範疇】 MOBILE(手持裝置)驅動晶片 【工作內容】 LCD driver(含OLED) Timing Control數位電路的研發設計與驗證 【需求條件】 1.熟悉HDL coding, simulation, synthesis, and STA flow,有量產經驗尤佳 2.熟悉LCD driver(或OLED)規格,具有相關工作經驗尤佳 3.熟悉Timing Control(Global Timing or SRC control timing or GIP timing)數位電路設計,有相關開發經驗者尤佳
09/11
新竹縣竹北市經歷不拘大學以上
a. Job Description: We are looking for a highly motivated RTL Designer to join our team in developing high-performance digital IPs. The ideal candidate will have experience in Register Transfer Level (RTL) design and verification, with a strong understanding of digital logic, microarchitecture, and ASIC/FPGA development processes. The role involves designing and verifying custom hardware IPs for cutting-edge applications. b. Verification: Develop and execute test plans to verify functionality, performance, and power requirements. Create testbenches using SystemVerilog/UVM for functional verification. Perform simulation, debugging, and root cause analysis for design issues. Conduct code coverage and functional coverage analysis to ensure comprehensive testing. Collaborate with verification and firmware teams to validate IP functionality. c. Qualifications: Bachelor’s/Master’s degree in Electrical Engineering, Computer Engineering, or a related field. 2+ years of experience in RTL design and verification. Proficiency in Verilog, SystemVerilog Strong understanding of digital design concepts, including pipelining, clock domains, and low-power design techniques. Experience with simulation tools (e.g., ModelSim, VCS, Questa) and formal verification techniques. Familiarity with UVM methodology and testbench development. Knowledge of scripting (Python, TCL, Perl, Shell) for automation. Experience with FPGA or ASIC development flows, including synthesis and timing analysis. Strong debugging and problem-solving skills. Excellent communication and teamwork abilities. - Non smoking
應徵
09/09
新竹市經歷不拘大學以上
【本職缺優先審核至高通官網投遞人選】請至高通官網上傳英文履歷表https://careers.qualcomm.com/careers/job/446706469752 【Talents who apply job through Qualcomm Career Website will be reviewed and considered as top priority】 https://careers.qualcomm.com/careers/job/446706469752 【The Potential Areas To Work Include】 • The main responsibility of this position is to do the performance analysis for world-class snapdragon CPU subsystem for mobile and portable computers. 【Minimum Qualifications】 • Master's, Electrical Engineering, Computer Engineering or Computer Science, emphasizing on computer architecture • Good knowledge on in-order/out-of-order CPU microarchitecture and architecture • Good knowledge on ARM bus protocol • Good knowledge on DDR subsystem • Good in C/C++ and scripting programming • Hands-on experience on performance analysis and validation works 【Preferred Qualifications】 • Experience in benchmark workload characterization and performance bottleneck analysis • Hands-on experience with performance verification on simulator or emulator • Familiar with ARMv8/v9 architecture • Knowledge of OS, firmware and software stacks • Familiar with GCC/LLVM compilation flow
應徵
09/09
創星電路設計股份有限公司其他電子零組件相關業
新竹縣竹北市經歷不拘學歷不拘
1. SerDes CTRL IP RTL 開發與維護 (例如LPDDR、UFS、NAND Controller...) 2. 設計驗證 3. FPGA相關設計與實作 以上工作依個人意願酌情分配
應徵
09/12
新北市新店區經歷不拘碩士
1.RTC Module/ IP design. 2.Design synthesis. 3.Design verification. 4.DFT/ siemens tools.
應徵
09/12
新竹縣竹北市經歷不拘碩士
1.Ethernet IP設計及修改 2.RTL邏輯電路設計、驗證、合成 3.SoC IP設計、修改及整合 4.FPGA
09/08
Paramtek_拚願科技股份有限公司電子通訊/電腦週邊零售業
台北市大安區經歷不拘碩士以上
1. 主動式電子掃描陣列 (相控陣列) 雷達系統之數位控制。 2. 熟悉Verilog與FPGA開發流程,了解High-Level Synthesis開發技術。 3. 具有實作數位訊號處理與數位架構設計於FPGA之經驗。
應徵
09/11
新竹縣竹北市4年以上碩士
1. (內轉佳, 提供發揮舞台, 跨產品線工作流程最佳化) 2. 人格特質: 領導力, 積極正面帶領團隊完成任務 3. 工作範圍:數位SOC設計整合, 包含 - Package, Floorplan, IOMUX, Test-mode design - Clock/CTS/reset/mixed-mode/DFT architecture, design and verification - RTL design and deliver SDC according to IP spec and requirement - SOC/IP DCT/DCG/Fusion synthesis - STA/CDC/CCD/TV/LEC/nLint/CLP tool and task handling
應徵
08/25
台南市永康區經歷不拘大學
1. 具有數位電路設計以及RTL coding基礎者 2. 熟悉EDA tool
應徵
09/08
台北市大安區經歷不拘大學
在宏成半導體,我們重視的是 態度、能力與學習意願,而不是任何單一的學歷或出身背景。過去我們曾與不同背景、不同專長的人才合作,他們都能在這裡找到發揮專長的舞台。 我們相信: 多元背景的人才 都能在這裡發揮價值。 重要的是 專注學習、願意承擔、樂於挑戰,而不是來自哪個學校。我們的研發方向屬於前瞻領域,團隊規模雖然不大,但每一位夥伴的努力都能 直接影響專案成果。因此,我們非常珍惜每一次面試機會,也希望雙方能在溝通時誠懇交流,確認彼此是否適合長期合作。 如果對公司的文化或制度有任何疑問,歡迎您在面試時直接提出,我們會誠實回應,並期待找到 真正志同道合 的夥伴,一起實現願景。 AI 邊緣運算 IC / IP 設計 RTL Coding / Functional Verification FPGA 驗證與系統整合
應徵
08/27
新竹市2年以上碩士以上
負責IP開發、整合與偵錯 -- 利用Verilog/SystemC從事邏輯設計與數位系統設計,以相關自動化軟體進行電路合成及模擬驗證,並配合利用FPGA系統平台進行系統整合與測試驗證。
應徵
09/12
瓦雷科技有限公司IC設計相關業
新竹市經歷不拘大學以上
[job description] Wolley is seeking candidates for a digital design engineer position. You will join an experienced team designing next-generation memory, storage controllers, and high-speed interface standard. You will also contribute to design concept discussion, architecture definition, as well as design implementation. ‧ Architecture design and RTL implementation ‧ System bus and related peripheral designs ‧ SoC and emulation platform design ‧ SoC system performance analysis [Requirement] 1. Bachelor's or Master's degree in Electrical Engineering or related fields 2. Familiar with RTL design, SystemVerilog, front-end design flow 3. The following working knowledge is desired: * Python programming * TCL scripting * Universal Verification Methodology (UVM) * Low power design and analysis
應徵
09/09
創星電路設計股份有限公司其他電子零組件相關業
新竹縣竹北市經歷不拘學歷不拘
1. SOC 整合 2. AMBA APB/AHB/AXI與類比IP模塊控制等周邊電路 3. CPU wrapper 4. FPGA相關設計與實作 以上工作依個人意願酌情分配
應徵
09/10
新竹市經歷不拘碩士以上
1. 實作開發TFT-LCD面板相關時序控制器 2. functions、algorithm相關 3. 對MOBILE(手持裝置)驅動晶片的數位IC設計工作有興趣者 4. 觸控IC、TDDI或指紋辨識IC開發經驗 5. MCU或DSP IC開發經驗 6. 工作地點:此職缺在【台南(樹谷園區)、新竹】皆設有相關單位,可依需求選擇工作地點