「PCB Layout 工程師【台元科技園區】」的相似工作

1.鋰電池BMS電路layout設計 2.確認電路PCB及FPC layout 3.開發新的軟性PCB及高速PCB的驅動板 4.相關layout文件處理 5.協助處理其他產品設計相關事宜 6.配合電子及機構工程師作業及主管交辦事項

Your Job Molex is seeking a Senior PCB Layout Engineer to join our Optical Solutions Business Unit (OSBU). In this role, the successful candidate will be part of a world-class engineering team, contributing to the design and development of next-generation coherent and PAM4 optical transceivers. The Senior PCB Layout Engineer will be responsible for creating high-speed, high-density PCB layouts that meet stringent signal integrity, power integrity, and thermal requirements. This role involves close collaboration with electrical, mechanical, optics and process integration engineers across global teams to ensure optimal performance, manufacturability, and reliability of our advanced optical transceiver modules. Our Team R&D Optoelectronic Solutions What You Will Do - Lead multi-layer PCB layout design for high-speed optical transceivers (e.g., QSFP-DD, OSFP). - Translate complex schematics into production-ready layouts using EDA tools. - Define layout constraints, stack-ups, and component placement in collaboration with cross-functional teams. - Support board bring-up and debug through layout reviews, lab measurements, and issue resolution. - Ensure compliance with DFM, DFT, and IPC standards; coordinate with vendors to address fab and assembly issues. - Generate and manage all fabrication and assembly outputs (Gerbers, ODB++, BOMs, drawings). - Mentor junior engineers and drive continuous improvement in layout processes and design practices. Who You Are (Basic Qualifications) - Bachelor's degree in Electrical Engineering, Electronics Engineering, or a related field. - More than 8 years of hands-on PCB layout experience in high-speed digital or optical communication products. - Proficient in Allegro PCB design software. - Strong knowledge of high-speed signal integrity, power integrity, PCB stack-up design, and layout best practices. - Experience with interfaces such as SerDes (e.g., 112G/224G PAM4), I²C, SPI, MDIO, and power delivery networks. - Familiarity with EMI/EMC mitigation techniques and thermal design considerations. - Solid understanding of PCB fabrication and assembly processes. What Will Put You Ahead - Experience with 800G & 1.6T optical transceiver PCB layout. - Familiarity with signal and power integrity simulation tools (e.g., Sigrity, Ansys, HyperLynx). - Previous involvement in volume production and high-reliability designs for data center or telecom applications.

1. 與客戶端進行技術/工程規格之討論與需求確認 2. 依客戶需求繪製電路圖 3. 依電路圖需求進行 PCB layout 4. 產出製作檔案給廠商，並討論工程問題 5. 協助專案產品除錯與功能驗證 6. 完成其他主管交辦事務 7. 需視案件時程彈性加班，確保專案進度與品質

在Gemini (APU) 晶片系列的設計中,做類比與數位IC佈局(Layout)和DRC, ERC, ANT, LVS之驗證, 該系列的晶片可提供高效率且廣泛的AI應用　　　　　

1.Layout Design 2.協助專案佈線,文字面等後續處理事宜 3.協助零件建立 4.完成工程師、主管交辦事項

1. PCB佈局、擺件、佈線 2. Design Rule & Allegro Constraint 設定 3. CAD/CAM檢查與Gerber輸出 4. 協助解決PCB設計、PCB製造及PCB組裝的各項工程問題

1. Analog mixed signal IC layout 2. 熟悉IC Layout tool 3. 熟悉先進製程

1.Analog and mixed mode circuit layout and verification 2.Co-work with designer for layout floor planning,routing and physical verifications 3.command file maintain

IC layout

We are seeking a highly skilled and motivated Field Application Engineer to provide advanced customer engineering support across our key semiconductor customers. This role will act as a critical technical interface between customers and our internal teams, focusing on problem solving, project execution, and proactive alignment with customer requirements and technology roadmaps. The successful candidate will play a hands-on role in delivering world-class technical support, ensuring rapid issue resolution, and strengthening long-term customer relationships. Key Responsibilities: 1. Advanced Technical Support · Provide expert-level advice on hardware requirements to enable successful loadboard/module design projects. · Conduct schematic capture, component placement, and routing support when needed to address complex technical challenges. · Act as a senior technical resource for diagnosing hardware-related feasibility and performance issues. 2. Customer Engagement & Relationship Building · Gather and validate customer requirements to ensure sufficient information for initiating design projects. · Serve as the primary technical contact, managing expectations and maintaining clear communication with customer engineering teams. · Manage customer interactions throughout the project lifecycle to ensure satisfaction and successful delivery. 3. Application Engineering & Solution Development · Assess and estimate project schedule, cost, and feasibility to define realistic plans. · Support design-in activities by translating customer requirements into technical hardware solutions. · Deliver technical updates, training, and presentations to customers and internal stakeholders. 4. Cross-Functional Collaboration · Collaborate with internal design and project management teams to align project execution with customer requirements. · Provide structured feedback from design projects to influence product development and continuous improvement. · Ensure alignment of project execution with both tactical problem solving and longer-term strategic direction. Preferred Traits: · Resilient and Professional Under Pressure – Remains calm and constructive when facing challenges, escalations, or changing requirements. · Proactive Problem Solver with Strong Ownership – Takes initiative, drives resolution, and ensures customer satisfaction while balancing immediate issue-solving with long-term improvements. · Collaborative and Organized Team Player – Demonstrates a positive “can-do” attitude, manages multiple priorities effectively, and works seamlessly with cross-functional and global teams. This job description serves as a general guide to the responsibilities and qualifications expected for the role and may be subject to modification based on the specific needs of the organization.

Role Summary/Purpose: Hardware design engineer will closely work with worldwide engineers to perform engineering works for hardware testing solution of next generation semiconductor devices. The work includes requirement analysis, feasibility study, solution evaluation, task planning, project management, design execution, quality control and verification. We are working on cutting edge requirement and future technology. Responsibilities: • Provide global semiconductor interface test hardware solutions of next generation semiconductor devices for world-wide customers • Provide chip test interface HW solution engineering to compare pros and cons of different approaches and recommend best option to customers considering both performance, lead time, cost • Responsible for Testing circuits Design and super high layers PCB design for high complexity ATE device interface board correspond to various device testing, eg. Mobile application processor, High performance computer, AI, RF etc. • Responsible for scheme selection of a SUBSTRATE/MLO design in wafer testing, research for low Cost of Test scheme (considering TDE, Skip DIE, substrate stack-up) • Responsible for power integrity (PI) and signal integrity (SI) simulation at board level or system level, frequency domain or time domain to ensure HW product performance at design stage • Implement complex mechanical design/simulation, cable design, thermal evaluation by collaborating with PCB design to achieve premium quality in hardware solution according to customer device testing ultimate challenges. • Responsible for global end to end hardware project management to ensure best quality and on time delivery -Device testing requirement assessment and Feasibility study -Risk analysis and mitigation planning -Schedule planning and project management -Design execution -Regular review with global internal and external customers -Quality Control and Verification • Work closely with Global supply chain, provide solution to solve manufacture (DFM), assembly (DFA) challenges, ensure hardware products on time delivery and very high first pass rate • New technology research, new products, new materials evaluation for next generation device testing • Deliver hardware design training and seminars to customers

1.客戶探針卡使用狀況回報 2.客戶端產品驗證及現場故障排除 3.受訓完畢之後，派駐於客戶端(台中or高雄) 4.擁有駐廠津貼、伙食及油資補助 【自我推薦獎金】 即日起，主動應徵本職缺，並到職滿三個月(試用過後成為正職員工)，可得獎金6,000元。 獎勵期間自即日起至2025/12/31，視招募情況可提前結束。

1. 負責IC版圖的自動佈局佈線、優化和驗證。 2. 確保IC佈局符合Circuit Designer設計需求及產品、製程、電氣的規範。

負責 3D-IC Interposer 與類比 IP 佈局設計 (Virtuoso / Allegro)，確保電性與實體規格，優化設計流程。 熟悉 Layout tools、Foundry PDK為佳。

【工作內容】 1.測試電路繪製與設計 2.案件排程掌握/協調 3.對客戶及對內的工程窗口 4.PCB layout 確認比對 5.電路除錯修改 6.特殊零件選購

1.依客戶需求設計PCB (Load board/BIB) 達成客戶所需交期 2.整合與改進Layout and PCB simulation 3.協助客戶解決PCB問題與技術支援 4.BOM表維護, PCB生產問題排除與追蹤 5.具良好團隊合作、溝通能力與學習力

【工作內容】 • 我們正在尋找具備先進製程經驗的 IC Layout 工程師，加入團隊後可以參與高階SoC /Analog IP 的實體實現，並負責以下工作： -Mixed-Mode FinFET Layout 設計與繪製，確保電路佈局在效能、面積與可靠性之間取得最佳平衡。 -進行 FinFET 製程相關的 DRC / LVS / ERC 驗證，確保設計符合法規與 Foundry 要求。 -熟悉 XRC & EM/IR 分析流程，進行可靠性評估，並針對潛在問題提出改善方案。 【職務條件】 • 必備條件：具備 FinFET 製程經驗，能獨立進行版圖設計與驗證。 -具備類比電路佈局經驗，了解電路特性與佈局考量，能與設計工程師密切合作。 -具備良好的溝通能力與團隊合作精神，能在專案時程內交付高品質成果。

1.各式文件管理 2.學習並執行相關SI專業 ◆◇誠摯邀請外向開朗、積極主動的您加入我們團隊，一同實現理想與抱負◆◇

1.對先進製程 IC Layout 有興趣者, 歡迎非本科系 2.熟悉EDA tools：Cadence Virtuoso,Laker,Calibre。 3.曾通過財團法人自強工業科學基金會IC佈局工程師培訓計畫 4.相關科系.有FinFET經驗者佳

AOI程式撰寫、MDA架設治具、FCT複測。