「資深IC實體設計工程師(APR)-新店」的相似工作

加入專業 IC 團隊，專責成熟製程的 Analog / Mixed-Signal 晶片開發與版圖設計，實作涵蓋 28nm 節點、ESD 保護與高速 Tx/Rx 模組，適合具備實務經驗並渴望技術突破的版圖工程師。 【工作內容】 • 使用 Laker 或 Virtuoso 進行 Analog / Mixed-Signal 電路之版圖設計 • 使用 Calibre 進行 DRC / LVS 等驗證作業 • 負責 28nm 等低電壓製程節點之 Layout 設計與優化 • 具備 ESD 與 Tx/Rx 電路 Layout 經驗者尤佳 • 與設計團隊密切協作，確保電路性能、面積、可靠度與製程規範之平衡 【職務條件】 • 具備 2 年以上 IC Layout 實務經驗 • 熟悉 EDA 工具：Laker、Virtuoso、Calibre（含 DRC / LVS） • 熟悉 Analog Layout 基礎與高階電路（含 LV、28nm） • 曾參與 IP 整合、版圖組裝與驗證流程 者佳 • 具備主動積極、細心耐心、具抗壓與團隊合作精神，能依時交付任務成果

1. Knowledgeable in power analysis and IR/EM methodologies, with hands-on experience using Ptpx, Redhawk, or Voltus for power and IREM evaluation. 2. Familiar with the integrated circuit (IC) design flow, capable of performing design, optimization, and verification using tools such as ICC2 or INNOVUS. 3. Experience in developing automation scripts using Python, Perl, TCL, or Shell is a strong plus. 4. Experienced in IO/IP planning, including bump/PAD placement and RDL routing is a plus. 5. Experienced in fundamental circuit structures (e.g., standard cells, IO), with the ability to simulate basic circuits using Hspice or Spectre is a plus.

1. Sub-block Layout. 2. Whole Chip IC Layout.

請務必投遞官網(13021): https://careers.synopsys.com/job/hsinchu/applications-engineering-staff-engineer/44408/87733350400 You Are: You are an innovative and resourceful engineer with a deep curiosity for solving complex technical challenges at the intersection of hardware and software. With a strong foundation in Electronic Engineering, Computer Science, or a related field, you are adept at leveraging your programming expertise—whether in Python, Tcl, Perl, or similar languages—to streamline and enhance engineering workflows. Your experience within UNIX/Linux environments equips you to navigate high-performance computing scenarios with ease. You thrive in collaborative, cross-functional teams and are energized by the opportunity to work closely with top-tier foundry partners and leading fabless companies. Your keen understanding of physical verification flows—such as DRC, LVS, PERC, FILL, and DFM—sets you apart, and you are eager to deepen your expertise in SoC physical design enablement, process effect analysis, and signoff. You are detail-oriented, capable of producing clear technical documentation, and communicate with clarity and empathy across diverse audiences. What You’ll Be Doing: 1.Delivering advanced physical verification solutions (DRC/LVS/PERC/Fill) for top-tier foundries and key fabless customers, ensuring high-quality silicon signoff. 2.Developing and validating process design kits (PDKs) and verification methodologies in collaboration with R&D and customer teams. 3.Partnering with R&D to innovate and improve Synopsys tools and flows, contributing to the evolution of physical verification technologies. 4.Providing hands-on customer support, troubleshooting issues, and delivering timely resolutions that enhance customer satisfaction and product adoption. 5.Coordinating with internal teams, including product managers and end-users, to align on best practices and ensure seamless integration of new technologies. 6.Documenting technical solutions, validation methods, and customer workflows for knowledge sharing and process improvement. 7.Staying up to date on industry trends and applying new insights to continuously optimize verification processes and tools. The Impact You Will Have: Accelerate the adoption and success of Synopsys physical verification products in leading-edge semiconductor manufacturing processes. Drive the development of robust PDKs and methodologies that enable customers to achieve first-time-right silicon. Enhance the quality and reliability of Synopsys verification tools through direct feedback and collaborative innovation with R&D teams. Strengthen Synopsys’ reputation as a trusted partner to top-tier foundries and fabless customers worldwide. Facilitate faster product cycles and reduced time-to-market for customers by delivering efficient and effective signoff solutions. What You’ll Need: BS or MS degree in Electronic Engineering, Computer Science, or a related field. Proficiency in at least one programming language, such as Python, Tcl, or Perl. Hands-on experience with UNIX/Linux environments and command-line tools. Familiarity with physical verification flows (DRC, LVS, PERC, FILL, DFM) and understanding of complex layout/electrical design rules. Strong investigative, analytical, and problem-solving abilities, with a passion for learning new technologies. Ability to produce clear, concise technical documentation and validation reports. Prior knowledge of tool/runset development/support and experience with SoC physical design is a plus.

We are seeking a highly motivated Design Verification Engineer to join our dynamic team. You will be responsible for ensuring the functional correctness of complex digital designs using industry-leading verification methodologies such as UVM, Formal Verification, and Coverage-Driven Verification. 【Key Responsibilities】 · Develop detailed verification plans based on design specifications and architectural documents. · Build and maintain System Verilog UVM-based testbenches for SoC/Subsystem/IP-level verification. · Write constrained-random and directed test cases to validate functionality, performance, and corner-case scenarios. · Perform coverage analysis (functional coverage, code coverage, assertions coverage) and drive towards coverage closure. · Apply Formal Verification techniques (e.g., property checking, connectivity checking) where applicable. · Support simulation regression runs and maintain automation scripts (Perl/Python/TCL/Makefile). · Participate in design and verification reviews, providing valuable feedback to improve quality.

● 開發與整合AI SoC核心模組（如記憶體與資料傳輸控制器）。 ● 設計高效匯流排架構，優化模組間資料傳輸性能。 ● 執行RTL設計、模擬與驗證，確保功能與時序符合要求。 ● 協助後端團隊進行時序分析與設計優化。 ● 撰寫技術文件，遵循高標準開發流程。

若有興趣者，請務必上傳英文履歷至官網,否則不予受理(職缺代碼12936): https://careers.synopsys.com/job/hsinchu/r-and-d-engineering-staff-engineer-zebu-12936/44408/87200702592 We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: A highly skilled engineer with a deep understanding of simulation, emulation, and compiler technologies. You bring extensive experience with HDL languages like Verilog and have previously worked with VCS and ZeBu platforms. Your proficiency in programming languages such as C/C++ is complemented by a strong grasp of data structures and algorithms, including graph theory. You excel in designing modular, scalable software architectures and optimizing software performance through multi-threading and operating system concepts. Your familiarity with version control systems like Perforce and Git enables you to manage code efficiently and collaborate seamlessly with other teams. You are an effective communicator, able to convey complex technical concepts clearly and work collaboratively in a dynamic environment. Your passion for technology drives you to stay updated with industry trends, and you actively mentor and guide junior engineers, fostering a culture of continuous learning and innovation. What You’ll Be Doing: 1.Designing and developing high-performance software for Synopsys' simulation and emulation platforms, including VCS and ZeBu. 2.Collaborating with cross-functional teams to enhance product capabilities and performance. 3.Conducting comprehensive research and analysis to address complex engineering challenges. 4.Leading project initiatives, ensuring timely and high-quality deliverables. Mentoring junior engineers and fostering a culture of continuous learning and innovation. 5.Integrating new technologies and staying abreast of industry trends to drive continuous improvement. The Impact You Will Have: 1.Enhancing the performance and reliability of emulation platforms used for cutting-edge silicon chips. 2.Driving the development of next-generation simulation and emulation tools. 3.Improving the usability and adoption of Synopsys products across various industries. 4.Contributing to a collaborative and innovative engineering culture within the team. 5.Advancing the future of technology and connectivity through continuous innovation. 6.Delivering high-quality, performance-optimized software solutions that elevate Synopsys' success. What You’ll Need: *CS or EE master's degree or above at least five of relevant experience. *Proficiency in programming languages: C/C++. *Strong understanding of data structures and algorithms, including graph theory. *Experience with hardware description languages like Verilog and scripting languages like TCL. *Prior experience with HDL simulation and emulation platforms, including VCS and ZeBu. *Familiarity with version control systems like Perforce and Git. *Ability to design and implement modular, scalable software architecture. *Proficiency in multi-threading and operating system concepts for software *performance optimization. Who You Are: A proactive and innovative thinker with a passion for technology. A collaborative team player who thrives in a dynamic environment. An effective communicator with strong interpersonal skills. A mentor and leader who inspires and guides junior engineers. A continuous learner who stays updated with industry trends and advancements.

1. 參與公司數位後段設計 之產品開發 2. 熟悉與維護 並參與 新流程之開發

【本職缺優先審核至高通官網投遞人選】請至高通官網上傳英文履歷表https://careers.qualcomm.com/careers/job/446705989572 【Talents who apply job through Qualcomm Career Website will be reviewed and considered as top priority】 https://careers.qualcomm.com/careers/job/446705989572 【General Summary】 As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm CPU Engineer, you will lead innovative Central Processing Unit (CPU) design efforts that have a critical impact on industries across the world. Qualcomm Engineers collaborate with cross-functional teams to design, verify, and implement multi-core CPU operations for all Qualcomm Business Units. 【Roles and Responsibilities】 • Collaborate with cross-functional teams (RTL, Physical Design, Circuits, CAD) to address critical physical design challenges in CPU implementations. • Develop innovative techniques within Physical Design and optimization space to meet stringent PPA targets. • Coordinate with CPU Software, Architecture, and RTL teams to understand various CPU use cases and propose impactful PPA optimizations. • Engage with external CAD tool vendors and internal CAD teams to identify and enhance optimization issues related to CPU designs. • Partner with all block-level implementation teams to analyze, implement, and improve optimization methods relevant to the designs. • Partner with Process, SoC and Post-silicon teams to analyze, improve design implementations. 【Must have skill/experience】 • Experience with Synthesis, place and route and signoff timing/power analysis. • Knowledge of high performance and low power implementation techniques • Proficiency in scripting (TCL, Python, Perl) 【Minimum Qualifications】 • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 6+ years of Hardware Engineering, Electrical Engineering, or related work experience. OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 4+ years of Hardware Engineering, Electrical Engineering, or related work experience. OR PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field and 3+ years of Hardware Engineering, Electrical Engineering, or related work experience.

1.類比/電源管理 IC電路設計. 2.參與LCD PMIC, LED Driver專案. 3.DC-DC, Charger-Pump, LDO, OP, DAC,ADC相關電路設計

歡迎2026年畢業並正在找尋研發替代役的同學申請! 職位選擇: Direction 1: Physical Design Engineer Direction 2: ASIC Physical Design Engineer Direction 3: DFX Engineer Direction 4: CAD Tools Development Engineer Direction 5: Design Verification Engineer What you’ll be doing: Key Domains: • Physical and ASIC Design Implementation • Backend and Layout Optimization • Design-for-Excellence (DFX: Test, Manufacturability, Debug) • Development of CAD/EDA Automation Tools • Functional and Formal Design Verification What we need to see: • MS degree from EE/CS or related majors from a prestigious university. • Good knowledge in digital circuit design. • Experience in using Verilog HDL. • Experience in various EDA tools. • Fluent in English reading and writing. • Self-motivated, good team player. Ways to stand out from the crowd: • Proven ability to work independently as well as in a multi-disciplinary group environment • Good command of C/C++ or Verilog programming language. • Familiar with Perl/Python/Tcl/Shell scripting 應徵方式: 請提供以下資料： • 英文個人履歷 • 學士+碩士成績單 (中英文皆可) 提交申請: 請將上述資料投遞至104，符合資格者將會收到進一步的聯繫通知。

【產品範疇】 Mobile/TCON - LCD display driver、OLED display driver Tablet - LCD display driver TV/NB -LCD display driver TCON 產品 【工作內容】 1.DRC/LVS Command file 撰寫&Maintain 2.Laker TF/UDD/PCELL 撰寫 3.PERC rule & 程式的開發 4.Analog design flow development 5.Shell/SKILL/TCL/Python 程式開發 6.新製程廠內的PDK development 7.In house Utility 開發 8.AI 輔助工具的開發與評估

1. SRAM library characterization flow. 2. SRAM library maintaining. 3. Develop and maintain automation flows for analog IC design.

Full Customer Layout

工作項目： 1. CPU & GPU Backend Implementation (APR) 2. CPU/GPU Backend Flow Development, Enhancement & Automation 3. Advanced CPU/GPU Technology Development: High-performance, Low Power, and PPA Optimization 應徵條件： 1. 碩士以上；電機、資工、電子相關科系畢業為主。 2. 熟悉 APR Tools (Innovus、ICC2、Fusion Compiler…)，有Synthesis、STA/IR Analysis、Physical Verification等相關經驗者佳。 3. 具備程式設計能力，熟悉 TCL/Perl/C++/Python。 4. 有 High Performance CPU/GPU APR經驗尤佳。 5. 個性積極負責、勇於迎接新挑戰，對於 High-Performance CPU/GPU Technology 有興趣者。

(1)Must have BS in CS/EE of relevant experience in IC design field. (2)Familiar with IC design flow, placement and route (P&R), and layout. (3)Circuit knowledge and logic design relevant experience would be a plus.

1.IC測試程式開發. 2.IC量產維護. 3.工程實驗 4.測試軟硬體模組開發. 5.主管交辦事宜.

Familiar with digital IC design verification flow is a plus. Familiar with SV/UVM is a plus. Familiar with PCIE/NVMe is a plus. You will be in charge of making testplan according to the specification. You will take participate in creating verification testbench, test writing/debugging, and regression convergence. We focus on the storage related IP and prospective features. We provide high flexibility with days off and competitive salary.

1.影像高速IP開發驗證相關工作 2.RTL coding/synthesis/simulation/verification

【工作內容】 • Work with team members and apply current functional verification techniques to perform and improve pre-silicon verification quality and product Time to Market • Provide the technical leadership to the DV team for the project • Work independently on various DV tasks and provide technical guidance to the DV team. • Be involved technically in the porting/creation of the DV environment for the new design, block and chip level test plan creation and implementation, coverage analysis, and regression cleanup 【職務條件】 • Master’s degree in Electrical Engineering, Computer Science, or related. • Good understanding of ASIC design verification flow. • RTL coding with Verilog/System Verilog and familiar with front-end design flow and C/C++ programming experiences. • Knowledge of Perl, OVL, SVA, SV, UVM, OVM, script programming, etc. 【其他條件】 • MSEE with a minimum of 5 years, or BSEE with a minimum of 8 years of experience in digital ASIC/SOC design verification • MS/BS degree in EE or CS with expertise in digital IP/SOC design verification.