「資深高速類比IC設計工程師 (High speed serial link)」的相似工作

【工作職責 (Responsibilities)】： ★ Build & innovate on high-speed analog/mixed-signal circuits such as PCIe/DDR/HDMI... transmitter and receiver in deep sub-micron CMOS technology for integration in SoC products. ★ Work with digital team on specification definition ★ Create behavior model for analog/digital evaluation ★ Compliance test for SerDes IP 【符合條件 (Qualifications)】： ★ Familiar with high speed SerDes specification ★ Familiar with IC/SoC design flow ★ Familiar with analog simulation flow ★ Experience SerDes analog blocks design ★ Must be good team player 【必須條件 (Minimum Qualifications)】： ★ Familiar with Audio analog IP design, such as Preamp/DAC/ADC (including SAR and DSM) 【優秀條件 (Preferred Qualifications)】： ★ Familiar with controller integration ★ Familiar with other baseband analog IP design, such as BGAP/LDO/XTAL/PLL, etc. ★ Familiar with ESD, Latch up, I/O ★ Familiar with layout flow

******以下有兩個不同的職位****** 【Analog IC Designer (DRAM IO) - 竹北】 工作內容 1. IO 設計. 2. DDR RX/TX 設計. 3. DDR 類比. 4. 擁有 DRAM IO 設計經驗，有 DDR5 以上經驗者尤佳。 擅長工具: HSPICE、Python、Laker、ADP、Custom Compiler 1. 學習過電子學、電磁學、電路學、工程數學等基本課程且成績優良。 2. Familiar with Analog Circuit Design 【 Analog IC Designer (Integration) - 竹北】 工作內容 1. Analog IP top integration, including projects of SSD/UFS/eMMC/SD 等。 2. 基本類比電路設計概念，例如 LDO、DCDC、BANDGAP、Voltage Detector 或 PLL、ADC 等。 3. 協助故障樣品分析與 IC 測試。 其他條件 1. 熟悉量產相關知識與經驗者佳。 2. 類比設計經驗超過 3 年。

Digital IC design engineer - Familiar with Verilog RTL coding - Familiar with digital design flow (pre-layout simulation, timing constraint, synthesis, post-layout simulation) - Will be working on high speed Serdes IPs - Experience or interest in all-digital PLLs or clock-data recovery circuits is a big plus

Job description Join our innovative team specializing in cutting-edge embedded memory solutions. We are seeking Analog Circuit Engineers to play a key role in the design and development of high-performance embedded DRAM and associated peripheral circuits. In this position, you will be responsible for the complete cycle of DRAM circuit design and simulation verification. Your tasks will involve developing novel circuit topologies, transistor-level design, optimizing performance metrics, and ensuring robust functionality through extensive simulations using industry-standard EDA tools. Required qualifications include a strong technical background in Electrical Engineering, Electronics Engineering, Computer Engineering, Physics, or a closely related field. Candidates must possess demonstrated, significant experience in DRAM circuit design and comprehensive simulation verification methodologies. Ideally, candidates will have proven design experience in specific DRAM-related circuit blocks, including but not limited to: Row and Column Decoder circuits Control path logic DC-DC converters, Charge Pumps, and Bandgap References Delay Locked Loops (DLLs) and Phase Locked Loops (PLLs) Negative voltage generators (NVG) and other critical peripheral circuits This is an excellent opportunity to contribute to state-of-the-art embedded memory designs in a dynamic, collaborative environment. If you are a skilled analog designer passionate about solving complex challenges in DRAM circuitry, we encourage you to apply and help shape the future of embedded memory technology.

1. SAR ADC / Current steering DAC/ SDM ADC/ DAC related 2. Analog Baseband related 3. 據有類比整合相關經驗佳

1、Mixed signal IC design and verification 2、Familiar with analog circuit designs including OPAMP/PGA, Analog active filter, ADC, DAC, level shifter, CDR, charge pump, PLL, bandgap reference 3、Co-work with board-level designers to analyze power and signal integrity of PCB. 4、Transmit signal & Noise characterization and analysis 5、Experience Preferred： 3-year work experience in the following fields High-speed serdes TX/RX application Pipeline ADC / SAR ADC 6.、Master or Ph.D. degree in EE

Do you expect to learn more the complete methodologies/solutions of design, implementation and analysis for a high-performance, power-efficient and area-effective chip developments? Do you also expect to explore the AI-driven solutions to accelerate chip design and improve efficiency throughout the design flow with AI-powered EDA tools? As part of our teams, you’ll have an opportunity to accordingly study, explore and design next-generation methodologies/solutions as follows. (1) Develop, maintain and optimize advanced methodologies for Frontend, Backend and Mixed-signal Design and implementation flows with the integrations of many corresponding EDA tools (Synopsys/Cadence/Siemens/Xilinx, ..., etc.) (2) Study, Explore and evaluate AI-driven design and implementation methodologies Currently, we expected this candidate is familiar with or interested in the related skill developments as follows. (1) Analog design flow and methodologies (Speed-up/Optimized simulation, mixed-signal co-simulation, EM/IR, Reliability Analysis, …, etc.). Knowledge of digital design flow using EDA tools (Synopsys, Cadence, Siemens (Mentor), …, etc.) is a plus (2) Programming/Scripting language like Perl, TCL, Python, C/C++, PERC, ..., etc. for flow automation (3) Be able to individually study and implement feasible solutions to resolve technical issues occurring in design and implementation flows. In our department, through kinds of flow developments and the related technical issue resolving, the following skill sets will finally be captured. (1) Extensive tool knowledge and experience for many different kinds of EDA tools and flow integration (Synopsys/Cadence/Siemens/Xilinx, …, etc.) used for Analog/Digital/FPGA Design and prototyping (2) Work with analog/digital design teams to coordinate a complicate project including Analog/Digital Designs for successfully tape out (3) Extensive AI-driven Analog/Digital/System Design and implementation flow We believe this position can be a great opportunity to extend your cross-fields IC design capabilities to include Analog, Digital and even System level designs for handling more complicate SoC design in the future.

Job desicription: Our Design Team specializes in the challenging field of Non-Volatile Memory (NVM) IC circuit design. We are actively seeking an experienced Analog Circuit Design Engineer to contribute to our cutting-edge developments in embedded NVM solutions and surrounding circuitry. As a key member of our team, you will be responsible for the design, verification, and debugging of essential analog building blocks like Bandgap references, LDOs, and Charge Pumps. A significant part of your role will involve designing critical memory peripheral circuits for NVM IP and test chips, including Array interfaces, Decoding logic, and Sense Amplifiers. Your responsibilities will span the design lifecycle, from contributing to IP specifications and core circuit design to ensuring performance through layout optimization and comprehensive corner simulations of NVM IPs. We are looking for candidates with proven expertise in analog circuit design, ideally with prior experience in embedded memory or NVM technologies. If you are an experienced analog designer eager to tackle complex challenges in non-volatile memory, we encourage you to apply and help shape the future of memory technology.

Hands-on experience in the design and development of at least one of the following analog circuits: ADC, DAC, PGA, high-speed analog driver, PLL, or SerDes.

1. PLL design 2. High speed receiver design (1.5Gbps/4Gbps/5.4Gbps/8.1Gbps/12Gbps) 3. High speed transmitter design (1.5Gbps/4Gbps/5.4Gbps/8.1Gbps/12Gbps) 4. eDP receiver 5. V-by-One receiver 6. MIPI D-PHY 7. HDMI Receiver 8. HDMI Transmitter 9. LCD P2P interface Transmitter 10. LDO and DCDC design 工作地點:新竹/台南

High speed interface serdes design(USB/HDMI/PCIe)

【成為円星人】 円星科技由一群專業與充滿熱情的夥伴創立於2011年，為積體電路矽智財設計服務業之新秀，秉持著『成為半導體業最值得信賴之IP公司』的願景，追求永續經營與成長。 誠摯歡迎您成為円星人，加入我們，站上國際舞台！ 一起共同打拚，以精品文化之精神，創造價值，追求卓越！ 【職務簡介】 M31主要業務為向 IC 設計業者和晶圓代工廠授權 IP，此職務為負責高速介面 IP（High Speed Interface IP）, 包含USB. PCIE, MIPI MPHY, CPHY, DPHY等SERDES IP和類比 IP（Analog IP）, 包含ADC, DAC, PLL, PVT sensor的類比IC設計工程師職缺。 【將負責的工作內容】 1. Mixed-Signal & Analog Circuits Design (LDO, OPA, Bandgap, ADC/DAC, etc) 2. High Speed Interface Analog Design (TX, RX, etc) 3. Clocking related：PLL/CDR 【條件與特質】 1. 有類比IC設計工程師相關工作經歷3年以上 2. 電機電子/資訊工程碩士畢業 如果您有以上相關經驗且對此職缺有興趣，歡迎投遞您的履歷！

RF及類比IC設計與整合： (1) VCO, PLL (2) PA, LNA, Mixer

工作職責 1.熟悉高速類比 SerDes 電路設計, 例如: CTLE, CDR, DFE, PLL, 以及 TX Driver 等 2.具有相關高速電路開發經驗 與熟悉Serdes 規格 3.加分條件: 具備有整合AI晶片與Serdes經驗 者 *************************************************************************** 如有興趣 若可以請準備個人履歷或相關作品說明 並將個人履歷資料上傳到以下網站 : https://ppt.cc/fPt3lx 檔案命名方式為 履歷檔案-名字-日期 比如 履歷檔案-張大明-2020815 檔案可以包成同一個壓縮檔) 若可以 內容盡量包含 : 1.大學碩士成績單 2.研究或專題論文 3. 其他可加分之書面資料 ***************************************************************************

USB Type-C PD/E-marked IC design

1. 具 0~2年數位晶片設計，或有 0~5年類比晶片設計工作經驗。 2. 具備基本數位和類比電路知識，熟習標準晶片設計流程。 3. 熟習業界常用EDA tools, 或Matlab/ Simulink。 4. 研習過CMOS or BiCMOS 類比設計電路課程，對放大器有基礎認識。 5. Experience in these areas is preferred： * BiCMOS or CMOS high-speed (>20Gb/s) circuit, Linear electrical amplifier & equalizer, High-speed (>25G) CDR/PLL/SerDes. * Linear optical laser driver & receiver (TIA + linear amplifier) 本職位負責類比IC電路的設計、驗證和除錯。這是一個高度技術性的職位，對公司的產品開發至關重要。我們正在尋找一位熱愛類比IC設計並具有相關經驗的人才，以推動公司的技術創新和發展。 如果您對這個職位感興趣，請投遞您的履歷表，我們立即與您聯繫。

1.Design and maintain analog circuits 2.Survey and maintain design processes 3.Survey and maintain design tools and flow 4.Help training junior engineers 5.Debugging and measuring chip

1. 有USB3.1 TX/RX PHY, CDR, PLL, CTLE, DFE, FFE 的經驗 2. MIPI PHY IP 設計經驗 3. Tapeout experience on 28nm or below 4. 技術指導及專案管理 *第1、2項經驗擇一即可

1.ADC/LVDSTRX/LVDSTX/MIPIRX/MIPITX/DC2DC/LDO/Charger/Power IC 2.類比電路特性量測 3.Analog/Mixed signal integrated circuit design

1.IO電路維護 或 ESD設計開發。 2.未來協助高壓元件及 IC ESD Plan 規劃。 3.未來訓練具維護簡易類比設計Analog Circuit IP 能力。 4.具獨立作業能力、態度積極主動並能協調Plan 規劃事務。