「資深高速類比IC設計工程師 (High speed serial link)」的相似工作

【工作職責 (Responsibilities)】： ★ Build & innovate on high-speed analog/mixed-signal circuits such as PCIe/DDR/HDMI... transmitter and receiver in deep sub-micron CMOS technology for integration in SoC products. ★ Work with digital team on specification definition ★ Create behavior model for analog/digital evaluation ★ Compliance test for SerDes IP 【符合條件 (Qualifications)】： ★ Familiar with high speed SerDes specification ★ Familiar with IC/SoC design flow ★ Familiar with analog simulation flow ★ Experience SerDes analog blocks design ★ Must be good team player 【必須條件 (Minimum Qualifications)】： ★ Familiar with Audio analog IP design, such as Preamp/DAC/ADC (including SAR and DSM) 【優秀條件 (Preferred Qualifications)】： ★ Familiar with controller integration ★ Familiar with other baseband analog IP design, such as BGAP/LDO/XTAL/PLL, etc. ★ Familiar with ESD, Latch up, I/O ★ Familiar with layout flow

Job Description: As a team member of analog product business group, this role will support Analog IC circuit design of mixed-signal ICs, such as sensors, motor drivers, data converters. Key Responsibilities: 1. Co-work with talented design teams to develop high performance sensor related integrated circuits and products, such as Hall effect sensor, temperature sensor. 2. Contribute to chip architecture and circuit design decisions 3. Collaborate with validation, product engineering and test engineering teams to enable successful transfer to production 4. Also, will be responsible for circuit requirements definition, design, simulation and analysis, layout/test support, documentation and customer support for sensor applications. Qualifications: 1. Demonstrate strong analytical and problem-solving skills 2. Strong time management skills that enable on-time project delivery 3. In depth working experience with Cadence composer and Virtuoso, Spectre, HSpice and mixed-signal design flow. 4. Experience in lab measurement and equipment. 5. Self-starter. Passionate about creative work. Good communication skills and team player. Able to take the initiative and drive for results.

1. 高速介面 (SerDes) 類比電路設計 2. Circuit design of CTLE/CDR/DFE/PLL/HDMI2.1 TX

Digital IC design engineer - Familiar with Verilog RTL coding - Familiar with digital design flow (pre-layout simulation, timing constraint, synthesis, post-layout simulation) - Will be working on high speed Serdes IPs - Experience or interest in all-digital PLLs or clock-data recovery circuits is a big plus

1. SAR ADC / Current steering DAC/ SDM ADC/ DAC related 2. Analog Baseband related 3. 據有類比整合相關經驗佳

Hands-on experience in the design and development of at least one of the following analog circuits: ADC, DAC, PGA, high-speed analog driver, PLL, or SerDes.

The successful candidate shall possess the capability to design and analyze high speed, high performance analog / mixed signal circuits, including data converters, PLLs, and SERDES, in advanced CMOS FinFET technologies. She or he shall bring the design all the way to production. Imagine being part of a team that is fundamentally changing the way people communicate, the way they collaborate, the way they watch TV and explore the universe through the internet. Utilizing our uniquely differentiated technology, we have created an Intelligent Transport Network with more speed, capacity and scalability than ever before. Imagine a world with unlimited bandwidth. The network of tomorrow will allow for content and creativity limited only by the imaginations of its users. If this is something that interests you, that excites you, come take a look at a team not bound by large company obstacles and bureaucracy, where an idea today can be set in motion tomorrow. Come take a look at Infinera! Engaging in the high-speed analog circuit design, you have the chance to create the technical differentiation for Infinera to hold the market leadership. We together will revolutionize the era of efficient high speed transmission by building the cutting-edge circuitry. Your Key Responsibilities Would Include: Design, implement, and simulate the functionality and performance of various high-speed analog circuits, including the ADCs and DACs; Create the layout floor plans to optimize the overall performance; Supervise the layout activities and give concise guidelines to layout engineers, need to be hands on in drawing layout if necessary; Exploring the trade-offs of the different topologies and propose the best solution to achieve or exceed the requirements in terms of power/area/linearity/bandwidth, etc. Develop the analog testing plans and work with the PE/TE teams to characterize the functionality and performance of the products to ensure the quality; Need to support and comply with the team’s design methodologies and release flows. Mandatory Knowledge/Skills/Abilities: Must be extremely familiar with essential CAD tools, such as Cadence Virtuoso, Spectre, Incisive, Calibre, EMX, and Totem EM/IR, etc. Must have a proven tracking record of designing complex analog / mixed signal IPs or chips in deep submicron CMOS technologies. Must have experiences in bringing high performance analog IPs including but not limited to high-speed ADC, high-speed DAC, and high-frequency low-jitter PLL to production. Must have a decent understanding in CMOS analog / mixed signal design methodologies and circuit analysis; Must have a good understanding of device physics and the impacts of layout effects; Able to perform the behavioral modeling the blocks and circuits with Verilog-A or Verilog-AMS; Collaborative with other local or remote team members in a fast-paced professional environment. Preferred Knowledge/Skill/Abilities: Fluent in verbal and written communications; Independently resolves issues and conquer design challenges; Self-motivated and detail-oriented; Has the knowledge of (optical) communication theories and Matlab coding. Education and Experience Requirements: Minimum Requirement for Principal Design Engineer: M.S. in E.E. with 12+ years’ experience, or Ph.D. in E.E. with 8+ years’ experience

記憶體power system 設計 『具工作經驗者，薪資另議』

High speed interface serdes design(USB/HDMI/PCIe)

【成為円星人】 円星科技由一群專業與充滿熱情的夥伴創立於2011年，為積體電路矽智財設計服務業之新秀，秉持著『成為半導體業最值得信賴之IP公司』的願景，追求永續經營與成長。 誠摯歡迎您成為円星人，加入我們，站上國際舞台！ 一起共同打拚，以精品文化之精神，創造價值，追求卓越！ 【職務簡介】 M31主要業務為向 IC 設計業者和晶圓代工廠授權 IP，此職務為負責高速介面 IP（High Speed Interface IP）, 包含USB. PCIE, MIPI MPHY, CPHY, DPHY等SERDES IP和類比 IP（Analog IP）, 包含ADC, DAC, PLL, PVT sensor的類比IC設計工程師職缺。 【將負責的工作內容】 1. Mixed-Signal & Analog Circuits Design (LDO, OPA, Bandgap, ADC/DAC, etc) 2. High Speed Interface Analog Design (TX, RX, etc) 3. Clocking related：PLL/CDR 【條件與特質】 1. 有類比IC設計工程師相關工作經歷3年以上 2. 電機電子/資訊工程碩士畢業 如果您有以上相關經驗且對此職缺有興趣，歡迎投遞您的履歷！

We are seeking a skilled Analog IC Design Engineer with expertise in MIPI TX/ PLL design and sensor readout circuits. The ideal candidate will possess a strong foundation in analog design and a passion for developing cutting-edge solutions in a collaborative environment. 1.Design and implement MIPI TX and PLL circuits for high-speed data transmission. 2.Develop charge pump and LDO (Low Dropout Regulator) circuits to ensure efficient power management. 3.Design and optimize oscillator (OSC) circuits for precise timing applications. 4.Create sensor readout circuits, including CDS (Correlated Double Sampling), TDC (Time-to-Digital Converter), ramp circuits, DAC (Digital-to-Analog Converter), and comparators. 5.Collaborate with system engineers to define specifications and ensure alignment with overall project requirements. 6.Perform circuit simulations and analyses using tools such as Cadence, Spectre, or HSPICE. 7.Conduct design verification and validation through prototyping and testing. 8.Optimize designs for performance, power efficiency, and reliability. 9.Participate in design reviews and contribute to project documentation. 10.Provide support during the layout and fabrication process. Preferred Qualifications: 1.Familiarity with IP design principles. 2.Experience with mixed-signal circuits. 3.Knowledge of low-noise and high-speed design techniques.

工作職責 1.熟悉高速類比 SerDes 電路設計, 例如: CTLE, CDR, DFE, PLL, 以及 TX Driver 等 2.具有相關高速電路開發經驗 與熟悉Serdes 規格 3.加分條件: 具備有整合AI晶片與Serdes經驗 者 *************************************************************************** 如有興趣 若可以請準備個人履歷或相關作品說明 並將個人履歷資料上傳到以下網站 : https://ppt.cc/fPt3lx 檔案命名方式為 履歷檔案-名字-日期 比如 履歷檔案-張大明-2020815 檔案可以包成同一個壓縮檔) 若可以 內容盡量包含 : 1.大學碩士成績單 2.研究或專題論文 3. 其他可加分之書面資料 ***************************************************************************

1. 類比電路設計開發 2. 感測器元件開發與整合 3. 具CIS影像感測器相關類比IC電路設計驗驗者佳

【產品範疇】 1.Touch panel controller 2.TDDI 【工作內容】 1.Analog front-end design 2.ADC design 3.Switched-capacitor circuit design 4.負責layout floorplan規劃，與layout工程師合作完成相關驗證 【需求條件】 1.Device physics knowledge applied to analog IC design 2.Familiar with analog IC design flow 3.Familiar with Hspice or Spectre

RF及類比IC設計與整合： (1) VCO, PLL (2) PA, LNA, Mixer

1.IO電路維護 或 ESD設計開發。 2.未來協助高壓元件及 IC ESD Plan 規劃。 3.未來訓練具維護簡易類比設計Analog Circuit IP 能力。 4.具獨立作業能力、態度積極主動並能協調Plan 規劃事務。

1. 有USB3.1 TX/RX PHY, CDR, PLL, CTLE, DFE, FFE 的經驗 2. MIPI PHY IP 設計經驗 3. Tapeout experience on 28nm or below 4. 技術指導及專案管理 *第1、2項經驗擇一即可

1.Analog front-end design 2.ADC design(Pipelined, SAR, Delta-sigma ADCs) 3.Switched-capacitor circuit design 4. Low EMI techniques 5. Mixed-signal system integration & modeling 6.負責layout floorplan規劃，與layout工程師合作完成相關驗證

振生半導體股份有限公司 (Jmem tek) 專注於半導體相關矽智財，提供設計服務與硬體資安專利，保護硬體資訊安全。如果您希望參與一個充滿潛力和創造力的環境，歡迎您加入我們的團隊。 工作內容： 1.負責混合訊號電路設計與模擬（包含 ADC、DAC、PLL 等電路）。 2.設計與開發電源管理電路（PMIC），包含 Charge Pump、LDO、Bandgap 參考源等模組。 3.開發高壓電源（High Power Domain）與核心電壓域（Core Voltage Domain）間的介面與穩壓電路。 4.撰寫模擬驗證計畫，執行電路模擬（Transient, AC, Noise, Corner, Monte Carlo 等）並分析結果。 5.配合數位 IC 工程師完成 Mixed-Signal Top-level 整合與 SoC 系統整合工作。 6.參與實體設計流程，完成晶片整合、驗證與 Tape-out。 7.撰寫設計規格書、模擬報告與設計文件，確保開發流程完整性與可維護性。 我們期望您具備的條件： 1.電子、電機相關科系碩士以上學歷，具備類比或混合訊號設計背景。 2.具備 3 年以上類比 IC 設計實務經驗。 3.熟悉常用類比模組設計（如 OTA、Bandgap、Comparator、Reference、Voltage Regulator 等）。 4.熟悉混合訊號模擬與驗證工具（如 Cadence Spectre、HSPICE、AMS flow）。 5.熟悉 ESD/LVTS、Latch-up、Layout Matching 基本設計原則。 6.具備先進製程經驗（如 TSMC 16nm、12nm、7nm）者佳。 7.具備晶片整合與量產經驗者尤佳。 8.具備良好溝通能力，能與 Layout、數位設計與測試工程師有效合作。 相關報導： 量子電腦資安攻防戰！振生半導體首創PUF+PQC市場唯一最佳解方https://udn.com/news/story/7240/7917935 EE TIMES 報導：振生半導體引領IC安全創新 https://www.eettaiwan.com/videos/jmem-technology-leads-ic-security-innovation/ 2024台灣新創世界杯「振生半導體奪冠」　10月赴美爭百萬美元投資款 https://finance.ettoday.net/news/2786606 DIGITIMES Asia報導：Chip startup JMEM TEK safeguards data security with hardware-software solution https://www.digitimes.com/news/a20221223VL202.html

1.SERDES CMOS Circuit Design ( HDMI,DisplayPort, or USB3.0 ). 2.All Digital PLL Circuit Design.