「Video Codec and Streaming Software Engineer (A/V)」的相似工作

(1) 開發IP Camera Middleware (2) 開發video streaming 相關功能 (3) 整合AI演算法 (4) 開發IP Camera相關driver (5) 開發http server及Onvif

Summary: Seeking experienced Firmware Engineers. This position will be responsible for working with engineering teams to develop (1) IPMI for ROT feature and DeltaNext Standard and OEM customization support. (2) Storage products and features about Storage Server, SAS JBOD and NVMe JBOF. (3) RAID solution to as alternative solution of replace Intel VROC, and reduce the cost of HW RAID solution for bootable RAID for OS drive on AMD platform. Essential Duties and Responsibilities: - Develop IPMI and ROT related features - Develop BMC FW feature for GPU system or Storage system - Responsible for designing, debugging, porting, defining, developing, testing and maintaining new kernel feature of BMC/IPMI related software and firmware for Server System. - Responsible for designing, debugging, developing, testing, and maintaining new GPU management features for server system. - Responsible for designing, debugging, developing, testing, and maintaining SAS Expander Firmware and PCIe Switch Configuration for Storage system. - Work closely with the software and hardware teams to develop and integrate embedded code to work with a variety of devices (MCU, CPLD, FPGA, etc..). - Develop RAID Driver for Windows OS, or Linux OS.

Bring up new generations high-performance and low-power SoC for edge computer vision Security camera and network connection application to diverse new markets. At iCatch, we had strong multi-OS on SoC experience to bring up system with best real time performance and flexible network connection products. We actively seek candidates with strong background in Linux video streaming, network or performance optimization experience to join an exciting cross-functional team to deliver the next generation computer vision products. [Responsibilities] 1.Develop and maintain Linux application, kernel and device driver of Security Camera products. 2.Support customer issues debugging on Security Camera applications including video streaming, network application and camera functions. 3.Work closely with other teams, such as software, hardware, SDK teams and Quality assurance teams to develop schedule and deliver BSP on time with good quality. 4.System program development (Linux development environment and embedded software). [Minimum Qualifications] 1.A BS degree in Computer Engineering, Electrical Engineering, or Computer Science. 2.At least 1-2 years of embedded software development experience Knowledge of Real-Time concepts 3.Familiar with Embedded Linux system development. 4.Strong experience in C programming 5.Will to co-work with customers on MP support and design win. 6.Self-motivated, good attitude, skilled in meeting deadlines and work collaboratively in a team environment

Skill • Familiar with Jenkins setup and configuration for automated image builds • Proficient in Python & Shell scripting to integrate testing cases and set up environments. • Skilled with Git commands for environment setup and debugging. • Linux experience preferred (e.g., Ubuntu OS, kernel driver installation/debugging. • Knowledge of camera imaging fields (e.g., V4L2 or multimedia subsystems) is a plus. Nice to have • Jenkins experience: installing and setting up Jenkins. • CI/CD experience: setting up automated build systems to maintain image quality • Automation support: supporting and maintaining the automated validation system. • Camera-related software development: Working on drivers, tools, and/or scripts.

1. SOC/IP 整合工作，從RTL到 Netlist 2. clock tree structure design 3. Lint / CDC check / Synthesis/ DFT/ LEC

A Digital Image Signal Processing Software Engineer in Ambarella for researching and developing advanced traditional or AI-based ISP and realize them on Ambarella future chips. At the same time, you will also be responsible for customer support for image quality tuning/suggestion/discussion for their product. Key responsibilities: 1. Advanced AI image signal process research and development 2. Traditional digital image signal process research and development 3. Worldwide customer project image quality tuning support

Job Description: Microchip’s Wireless Solutions Group is seeking a FPGA engineer to support SOC development for our next generation, mixed signal, wireless products. The role will focus on the areas of RTL design, FPGA synthesis and FPGA system bring-up, debug and validation. It will require a proactive candidate with a proven record of success in cross functional and cross site team environments. Key Responsibilities: • Collaborate with the design team to develop and optimize the RTL for FPGA , ensuring its efficiency and functionality. • Conduct FPGA synthesis using industry-standard tools to transform RTL code into a target FPGA device. • Assist in the initial bring-up of the FPGA system, ensuring proper functionality and identifying and resolving any issues that may arise. • Perform through testing and validation of the SOC design, both at the RTL level and in the FPGA implementation, and resolve any bugs or issues that are discovered. • Collaborate closely with the FW (Firmware), Validation, and RF teams to successfully carry out FPGA system bring-up, debug, and validation activities.

[Responsibilities] ★ Experienced in ISP (Image Signal Processing) ★ Plan design architecture. ★ Develop high quality digital design. ★ Be familiar with IC design flow. [Minimum Qualifications] ★ Outstanding problem analysis and debugging skills. ★ Experienced in C language. ★ Experienced in Verilog RTL language ★ Experienced in digital IC design front-end flow ★ Experienced in CAD tool usage such as simulation tool, linting tool, synthesis tool, member compiler [Preferred Qualifications] ★ Nice to have experiences in scripting language. ★ Nice to have experiences in FPGA flow

影像處理IP設計開發。 【應徵條件】 1. 具Image/Video 影像處理算法設計開發經驗 (1)影像優化 (2)色彩處理 (3)影像壓縮 2. 具LCD/OLED影像處理算法設計開發經驗 (1)面板demura處理演算法 (2)補償面板缺陷 (3)優化面板顯示效果 3. 熟悉C/C++/Matlab 4. 熟悉OLED驅動原理尤佳

工作項目： 1. Camera firmware 負責同仁，專門處理 Tier 1 Customer firmware的需求 2. Camera firmware 底層開發，專門處理 Customer function 到 Git 的整合和標準化 3. Camera AI feature開發，專門處理Customer的AI應用 應徵條件： 1. 碩士以上，電機工程、電信工程、電控工程、電子工程、資訊工程、資訊科學、動力機械、自動控制、通訊工程相關科系畢業為主 2. 熟悉 C , C++ , Python , Git, Python 3. 熟悉 Scope , USB Analyzer , I2C Analyzer 4. 具3年以上下列相關經驗者佳： -熟悉 USB 協議和相關產品及USB Camera 相關 firmware 控制 -熟悉 firmware code compiler 環境及控管軟體 -了解 Camera ISP Pipeline 及 PC Camera相關 feature -具備基本 Hardware debug (GPIO / I2C etc..) 能力 相關經驗者為佳。

1. Fine-tune image quality for projects and communicate with customer 2. Production line calibration tool maintenance and development 3. 3A maintenance

The Team and Role: Position at Logitech PWS (Personal Workspace solution) engineering group The Personal Workspace Solution group from Logitech is committed to help people create and communicate their passion and work to the world, anytime anywhere. Putting users front and center, we strive to innovate and elevate their experiences. This is more than computer mice, keyboards, webcams and presentation remotes - it’s about enabling the future beyond today's tools and in a sustainable way. Everything goes through great design and exceptional user experience conveyed in great hardware and elevated by software. As Senior Camera Firmware Engineer , you will define, develop, implement, test, and sustain firmware for next-generation video-enabled platforms at Logitech. In this role, you will work closely with cross-functional teams, partners, and vendors to craft and deliver robust firmware platforms for industry-leading webcams. Your contributions will elevate the overall performance, security, quality, and scalability of Logitech’s video communication products, supporting both innovation and product lifecycle needs. Your Contribution: Be Yourself. Be Open. Stay Hungry and Humble. Collaborate. Challenge. Decide and just Do. Share our passion for Equality and the Environment. These are the behaviors and values you’ll need for success at Logitech. In this role you will: • Contribute to the design and implementation of 3A (AF, AE, AWB) algorithms on the target platform. • Design, develop, debug, and test firmware for embedded platforms running Linux or RTOS, ensuring optimal image quality and performance. • Collaborate with cross-functional teams to define and deliver firmware solutions for new webcam products, sustain existing products, and drive forward innovation projects. • Create distinctive features that elevate product capabilities and enhance user experiences. • Work closely with the Software team to develop and deliver new features that enrich the overall user experience of the product.

【About the role】 Hytech is seeking a forward-thinking Manager of Software Security Architecture to lead the strategy, development, and execution of a world-class application security program. This highly technical leadership role will define the vision for embedding security throughout the software development lifecycle (SDLC), including modern AI and machine learning platforms. The ideal candidate will have deep expertise in secure software development, application security engineering, CI/CD automation, and integrating security into traditional, cloud-native, and AI-enabled environments. You will lead a global team of security engineers, build scalable developer-focused security solutions, and shape security strategies across engineering, infrastructure, DevOps, and data science teams. What this job involves: [Program Ownership & Strategy]: 1. Own and advance the enterprise application security program, including vision, technical strategy, and execution. 2. Define and implement scalable, modern AppSec practices for cloud-native and AI-enabled development. 3. Represent application security in enterprise architecture, risk, and compliance initiatives. 4. Define KPIs to measure security posture and program effectiveness. [Leadership & Collaboration]: 1. Lead, mentor, and grow a global team of application security engineers and specialists. 2. Promote a proactive “shift-left” culture by embedding security throughout the SDLC. 3. Partner with development, DevOps, AI/ML, and product teams to integrate secure practices into software and data science workflows. 4. Build strong cross-functional relationships to drive security-first thinking and align investments with business value. [Security Tooling & Technical Implementation]: 1. Drive adoption and optimization of security tools (SAST, DAST, SCA, IAST, secrets scanning, etc.) in CI/CD workflows. 2. Design and deploy developer-friendly tools for threat modeling, code scanning, secrets detection, and dependency analysis. 3. Implement internal secure-by-default frameworks and reference architectures. [AI/ML Security]: 1. Collaborate with AI/ML teams to implement secure design patterns for model development, training pipelines, and service deployment. 2. Develop and enforce security controls for AI applications, including data integrity, robustness, governance, and prompt injection prevention. 3. Evaluate and integrate emerging tools for securing ML pipelines, generative AI models, and AI APIs. [Security Enablement, Education & Documentation]: 1. Build scalable security enablement programs, including secure coding workshops, bootcamps, and self-service resources/platforms. 2. Develop and maintain internal security documentation, policies, and standards. [Research & Continuous Improvement]: 1. Stay current on application security threats, AI security research, and best practices in cloud and software engineering.

ASIC design engineer responsible for post-RTL design flow. He/She will be responsible for block and /or chip level synthesis, timing closure, DFT generation, and ECOs. The responsibilities include but are not limited to. •    Improve the design methodology and flow. •    Synthesis, timing closure, and DFT support for various types of SerDes IPs ranging from 10Gbps to 224Gbps data rates for different applications. •    Collaborate with Analog/Digital design teams to deliver competitive SerDes IP solutions for all the Marvell product lines. •    Provide support to the product teams, for both pre and post-silicon

1. 建置與維護 CI/CD pipeline，確保軟體能快速、穩定地整合與部署 2. 與開發團隊及SQA協作，提升開發到測試的自動化程度 3. 維護與優化版本管理流程 (Git branching strategy, tag/release pipeline) 4. 撰寫並維護自動化腳本 (Shell, Python, etc.) 5. 支援團隊落實 DevSecOps，強化安全性檢查 (e.g. SAST/DAST, dependency scanning, coding style) 6. 與相關系統整合, 如Github, JIRA, Jenkins, SonarQube, etc.

1. 具 0~2年數位晶片設計，或有 0~5年類比晶片設計工作經驗。 2. 具備基本數位和類比電路知識，熟習標準晶片設計流程。 3. 熟習業界常用EDA tools, 或Matlab/ Simulink。 4. 研習過CMOS or BiCMOS 類比設計電路課程，對放大器有基礎認識。 5. Experience in these areas is preferred： * BiCMOS or CMOS high-speed (>20Gb/s) circuit, Linear electrical amplifier & equalizer, High-speed (>25G) CDR/PLL/SerDes. * Linear optical laser driver & receiver (TIA + linear amplifier) 本職位負責類比IC電路的設計、驗證和除錯。這是一個高度技術性的職位，對公司的產品開發至關重要。我們正在尋找一位熱愛類比IC設計並具有相關經驗的人才，以推動公司的技術創新和發展。 如果您對這個職位感興趣，請投遞您的履歷表，我們立即與您聯繫。

無人機控制、資料傳輸之APP開發 工作技能((Android)： 【Android】- java或kotlin需會其中一種或都會更佳

Responsibilities • Responsible for authoring firmware specifications, design and developing EDKII firmware code, debugging and troubleshooting potential issues • Responsible for firmware related issues during the planning, development, and validation stages of the program through a product's lifecycle • Study new technical specifications and provide guidance/training accordingly • Work closely with cross-functional teams in silicon, core, QA and customer teams • Work closely with silicon vendor for problem analysis and resolution • Attend meetings based on customer's needs to overlap US or TWN time

About us: VICI Holdings' Hardware team is seeking a skilled FPGA Engineer to join our dynamic group. In this role, you will be pivotal in advancing our trading systems, contributing to the development and enhancement of cutting-edge technologies. We boast the leading software development team in Taiwan and possess FPGA design technology in parallel with wall street trading firms. This expertise enables us to build low-latency, fully automated trading systems. Our trading strategies cover stocks, futures, and derivatives, achieving a daily global trading volume in the hundreds of millions dollars. Roles/ Responsibilities: • High speed IP interface design (such as PCIE gen 3, 4 / Ethernet, DDR etc.) • In charge of FPGA design/ implementation/simulation. • Transmission protocol layer development. • Optimizing hardware for latency. • Proficiency with Xilinx design environment. Candidate Requirements: • BS/MS degree above from EE, CE with 2+ years of relevant work experience • Experience in high-speed interface design or knowledge in PCIE/ Ethernet/MIPI/DDR design or implementation is a plus • Experience using System Verilog and at least two prior RTL design is a required. • Demonstrated ability to tackle complex design challenges and implement effective solutions Other Requirements: • High self-motivated individual with good communication skill. • English level – working level proficiency is a plus. Interview Process: • Resume selection ->Coding Test -> AI Interview (Online) -> F2F Interview -> HR Manager

1. 具一年以上韌體開發經驗(程式語言 C / C++) 2. 熟悉 CANBUS, RS232/485, Ethernet相關介面開發 3. 熟悉 ARM Cortex-M /A 相關開發環境與程式設計。 4. 負責產品韌體功能程式維護、測試。 5. 與硬體工程師合作，進行新產品技術研究測試驗證。