「Video Codec and Streaming Software Engineer (A/V)」的相似工作

(1) 開發IP Camera Middleware (2) 開發video streaming 相關功能 (3) 整合AI演算法 (4) 開發IP Camera相關driver (5) 開發http server及Onvif

1. SOC/IP 整合工作，從RTL到 Netlist 2. clock tree structure design 3. Lint / CDC check / Synthesis/ DFT/ LEC

We are seeking (Sr.) Software Engineers for Zhonghe（中和）/TaoYuan Bade （桃園八德） Office. We need some excellent software design engineers for the development of more valuable and advanced software features and support more broad range of MB/Chassis/System. 1. Server management software design, implement and validate. 2. Innovate competitive server management software features. 3. Leveling up and automating server management services. 4. Sorting complex server firmware/hardware functionalities. Present functionalities with simple and friendly user interface. 5. Troubleshoot issues and provide solutions. 6. Preferred programming language: C++/C/Golang 7. Supporting OS: Linux/Windows/Unix/Hypervisors.

A Digital Image Signal Processing Software Engineer in Ambarella for researching and developing advanced traditional or AI-based ISP and realize them on Ambarella future chips. At the same time, you will also be responsible for customer support for image quality tuning/suggestion/discussion for their product. Key responsibilities: 1. Advanced AI image signal process research and development 2. Traditional digital image signal process research and development 3. Worldwide customer project image quality tuning support

* 搭建測試環境，包含設備、網路架構、嵌入式系統。 * 手機用 Camera 相關 SoC 之畫質調整 & 協助相關影像的自動測試。 * 手機用 Camera 的 SoC 方案影像品質調整。 * Camera 3A 調較 (自動對焦、白平衡、自動曝光 )。 AE/AWB/AF 演算法實作應用參數調整。 * 影像品質調校 (雜訊處理、解析度提升、背光補償、寬動態)。 Camera ISP 流程實作。 * 影像品質驗證 & 參數調整，影像品質改進 & 應用 。 配合軟體團隊進行圖像效果調試 & 優化。 * 設計測試驗證 & 相關問題排除 (debug)。 協助 BU & RD 部門解決測試相關問題，並依需求執行實驗、數據分析 & 報告撰寫。 持續優化測試流程 & 方法，降低產品重測率，提高測試效率。 * 支援 Camera 相關問題的分析 & 解決。 1. Manage final Image Quality Tuning of Smartphone camera. 2. Set up required tests for validating Image Tuning. 3. Engage with different Sensors and Module solutions and incorporate the new technology into company products. 4. Work with different generation SoC or RD/SW engineers to integrate the algorithms onto their platforms. 5. Qualified Tuning Engineer on each area (one of AE/AWB/AF/ISP) would also have below additional responsibilities 5-1. Technical training, support and result review for Jr. engineers 5-2. Evaluate the appropriate task ETA date on each specific area (one of AE/AWB/AE/ISP) 6. Annual salary: 800K NTD and above 7. Onsite Google Xindian Office Smartphone Camera Image Quality Tuning Engineer (IQT) Ref. • AE (Auto Exposure) • AWB (Auto White Balance) • AT (Auto Focus) • ISP (Image Signal Process) • SoC (System on a Chip) • ETA (Estimated Time of Arrival) • HD (High-Definition) • SD (Standard-Definition) • HDR (High Dynamic Range) • DSLR (Digital Single-lens Reflex) • ISP (Image Signal Processor)

1. Fine-tune image quality for projects and communicate with customer 2. Production line calibration tool maintenance and development 3. 3A maintenance

[Responsibilities] ★ Experienced in ISP (Image Signal Processing) ★ Plan design architecture. ★ Develop high quality digital design. ★ Be familiar with IC design flow. [Minimum Qualifications] ★ Outstanding problem analysis and debugging skills. ★ Experienced in C language. ★ Experienced in Verilog RTL language ★ Experienced in digital IC design front-end flow ★ Experienced in CAD tool usage such as simulation tool, linting tool, synthesis tool, member compiler [Preferred Qualifications] ★ Nice to have experiences in scripting language. ★ Nice to have experiences in FPGA flow

1. 熟悉自家晶片系統, 能根據客戶需求開發可商業量產的AI model, 包含dataset收集標註, Training, Simulation, 並在自家系統的EVK板端撰寫C程式驗證結果, 並完成系統測試與整合. 2. 協助客戶使用自家開發的 machine learning 套件,online training, 並處理客戶使用上的問題, 例如AI model轉換問題, 或是轉換前後的精度問題. 3. 撰寫test case , 在自家開發的EVK系統上 跑auto test來驗證穩定性. 4. 協助sale or marketing人員準備AI相關的展示, 向客戶介紹推銷自家的SOC. 5. 協助maintain現有的AI算法,或是將算法移植到其他自家SOC上.

Job Description: Microchip’s Wireless Solutions Group is seeking a FPGA engineer to support SOC development for our next generation, mixed signal, wireless products. The role will focus on the areas of RTL design, FPGA synthesis and FPGA system bring-up, debug and validation. It will require a proactive candidate with a proven record of success in cross functional and cross site team environments. Key Responsibilities: • Collaborate with the design team to develop and optimize the RTL for FPGA , ensuring its efficiency and functionality. • Conduct FPGA synthesis using industry-standard tools to transform RTL code into a target FPGA device. • Assist in the initial bring-up of the FPGA system, ensuring proper functionality and identifying and resolving any issues that may arise. • Perform through testing and validation of the SOC design, both at the RTL level and in the FPGA implementation, and resolve any bugs or issues that are discovered. • Collaborate closely with the FW (Firmware), Validation, and RF teams to successfully carry out FPGA system bring-up, debug, and validation activities.

Responsibilities • Responsible for authoring firmware specifications, design and developing EDKII firmware code, debugging and troubleshooting potential issues • Responsible for firmware related issues during the planning, development, and validation stages of the program through a product's lifecycle • Study new technical specifications and provide guidance/training accordingly • Work closely with cross-functional teams in silicon, core, QA and customer teams • Work closely with silicon vendor for problem analysis and resolution • Attend meetings based on customer's needs to overlap US or TWN time

The Team and Role: Position at Logitech PWS (Personal Workspace solution) engineering group The Personal Workspace Solution group from Logitech is committed to help people create and communicate their passion and work to the world, anytime anywhere. Putting users front and center, we strive to innovate and elevate their experiences. This is more than computer mice, keyboards, webcams and presentation remotes - it’s about enabling the future beyond today's tools and in a sustainable way. Everything goes through great design and exceptional user experience conveyed in great hardware and elevated by software. As Senior Camera Firmware Engineer , you will define, develop, implement, test, and sustain firmware for next-generation video-enabled platforms at Logitech. In this role, you will work closely with cross-functional teams, partners, and vendors to craft and deliver robust firmware platforms for industry-leading webcams. Your contributions will elevate the overall performance, security, quality, and scalability of Logitech’s video communication products, supporting both innovation and product lifecycle needs. Your Contribution: Be Yourself. Be Open. Stay Hungry and Humble. Collaborate. Challenge. Decide and just Do. Share our passion for Equality and the Environment. These are the behaviors and values you’ll need for success at Logitech. In this role you will: • Contribute to the design and implementation of 3A (AF, AE, AWB) algorithms on the target platform. • Design, develop, debug, and test firmware for embedded platforms running Linux or RTOS, ensuring optimal image quality and performance. • Collaborate with cross-functional teams to define and deliver firmware solutions for new webcam products, sustain existing products, and drive forward innovation projects. • Create distinctive features that elevate product capabilities and enhance user experiences. • Work closely with the Software team to develop and deliver new features that enrich the overall user experience of the product.

1. IC驗證 2. BSP Driver開發與驗證 3. Display Driver開發與驗證 4. Video Driver開發與驗證 5. Audio Driver開發與驗證 6. 協助客戶完成客製化需求

ASIC design engineer responsible for post-RTL design flow. He/She will be responsible for block and /or chip level synthesis, timing closure, DFT generation, and ECOs. The responsibilities include but are not limited to. •    Improve the design methodology and flow. •    Synthesis, timing closure, and DFT support for various types of SerDes IPs ranging from 10Gbps to 224Gbps data rates for different applications. •    Collaborate with Analog/Digital design teams to deliver competitive SerDes IP solutions for all the Marvell product lines. •    Provide support to the product teams, for both pre and post-silicon

1. 建置與維護 CI/CD pipeline，確保軟體能快速、穩定地整合與部署 2. 與開發團隊及SQA協作，提升開發到測試的自動化程度 3. 維護與優化版本管理流程 (Git branching strategy, tag/release pipeline) 4. 撰寫並維護自動化腳本 (Shell, Python, etc.) 5. 支援團隊落實 DevSecOps，強化安全性檢查 (e.g. SAST/DAST, dependency scanning, coding style) 6. 與相關系統整合, 如Github, JIRA, Jenkins, SonarQube, etc.

影像處理IP設計開發。 【應徵條件】 1. 具Image/Video 影像處理算法設計開發經驗 (1)影像優化 (2)色彩處理 (3)影像壓縮 2. 具LCD/OLED影像處理算法設計開發經驗 (1)面板demura處理演算法 (2)補償面板缺陷 (3)優化面板顯示效果 3. 熟悉C/C++/Matlab 4. 熟悉OLED驅動原理尤佳

軟體人才赴日工作職缺 【應徵方式】 可直接投遞履歷，我們會再介紹所有適合您的職缺。 ①待投遞完成後，專員會提供日文履歷供您填寫 ②履歷確認後會安排線上面談並介紹工作給您 -------------------------------------------------------------------------------- 【職務內容】 ・網站開發相關 ・ERP/CRM開發相關 ・APP開發相關 ・企業系統開發相關 【工作地點】 ・東京/日本全國 【薪資待遇】 ・年薪400日圓～800萬日圓 【應徵條件】 ・日文具備日常會話程度（N2以上） ・有兩年以上相關經驗

* 搭建測試環境，包含設備、網路架構、嵌入式系統。 如: 自動化測試流程（CI/CD Pipeline 測試)。 * 手機用 Linux 相機 drive 測試。 執行 camera 模組測試案例（Test cases）並建立高效的測試流程。 * 全面測試手機用 Camera 模組的各項功能。 * 在實驗室內 & 室外進行客觀測試，將測試條件拍攝後收集資料計算 & 整理測試數據報告。 分析測試結果，記錄與追蹤問題 (Issue tracking)，與開發團隊協作進行 debug。 運用 Jira/Bugzilla 對 Camera 開發專案中的 bug 進行追蹤 & 管理。 協助研發工程師對 bug 進行分析定位，提高 camera 影像質量。 * 負責維護 & 改善測試流程。 * 負責維護 & 更新試驗室設備。 * 需要會 Python，懂 Linux 的 OS，執行 Script 測試或修改。 1. Set up required tests for validating Image Tuning. 2. Provide Manual & Automated Testing support for the Camera team by capturing photos and videos using the Mobile Devices during the development phase and provide feedback on comparisons with other flagship devices in the industry. 3. Provide consistent and qualitative feedback to the engineering on the preferred tuning direction. 4. On demand Data Collection and Camera update verification. 5. Operate Lab Lighting equipment to capture Lab Images and run the evaluation tools. 6. Capture Real Life Images with different devices for Image Data collection, Image Quality Testing and Evaluation. 7. Generate Image Quality Reports based on the collected images/videos and provide feedback to the engineering teams. 8. Collect the Debug data, Raw images, log and/or Video to help debug and improve the feature repeatedly. 9. Collect Videos for feature evaluation and system performance. 10. Organize captured data and do initial evaluation and camera performance evaluation. 11. Collect Images and Videos of several Lighting conditions and environments. 12. Collect people's Images and provide image quality qualitative and quantitative feedback. 13. Labeling data for new and existing features (such as pictures, videos, etc.) 14. Planning the verification of new algorithm or parameters 15. To do face trigger for mobile phone camera tests or image database capture. 16. Organize test results and image database. 17. Image database management in Python. 18. Write simple scripts to automate the test process in Python. 19. Write documents in English such as test procedures. 20. Occasionally required to work at night or weekend for mobile phone camera tests. May need to travel to Hsinchu, Taoyuan or Taipei city for tests. 21. Annual salary: 800K NTD and above 22. Onsite Google Banqiao Office Smartphone Camera Testing Engineer Ref. • AE (Auto Exposure) • AWB (Auto White Balance) • AT (Auto Focus) • ISP (Image Signal Process) • HD (High-Definition) • SD (Standard-Definition) • HDR (High Dynamic Range) • DSLR (Digital Single-lens Reflex) • ISP (Image Signal Processor)

【產品線描述】 專注於提供高效能高品質的IC解決方案，涵蓋TV SoC及ASIC領域，並透過深厚的軟體技術優勢，確保產品的市場競爭力。 ■ TV SoC 軟體解決方案： 智慧電視系統整合、影像與音訊處理優化、AI 影像增強、多媒體與串流服務支援 ■ ASIC 軟體解決方案： 高效能低功耗設計、相機與影像處理技術、深度學習推理引擎、高效能計算架構、開發工具鏈 【工作說明】 1. 軟韌體開發 2. 協同客戶開發建構Smart TV 系統 3. 單晶片系統整合 【必要條件】 1. 碩士以上，電子、電機、資工、控制.. 等理/工學院相關科系畢業 2. 具備程式開發能力 3. 能配合工作需求出差

1. 根據 Device Driver功能需求, 使用 C/C++開發 Test Program for Unit Test and Integration Test 2. 撰寫 test case測試 TV 功能 3. 維護既有 TV 平台及維護新開發功能

Job Title: NPU Modeling Engineer Job Description: Overview: We are seeking an experienced NPU Architect to join our team. As an NPU Architect, you will play a crucial role in designing and implementing the hardware model for our Neural Processing Unit. Your expertise will be instrumental in ensuring efficient and accurate execution of neural network workloads on our NPU. Responsibilities: 1. NPU Architecture Design: • Collaborate with cross-functional teams to define the architecture and specifications for the NPU. • Design the NPU's core components, including the PE array, memory hierarchy, and control logic. • Optimize for performance, power efficiency, and scalability. 2. Bit-True Hardware Model Implementation: • Develop a bit-true hardware model of the NPU in C language. • Ensure that the model accurately represents the NPU's behavior, including arithmetic operations, memory access, and control flow. • Validate the model against reference neural network workloads. 3. Cycle-Accurate Modeling: • Create a cycle-accurate model of the NPU to simulate its behavior at the clock cycle level. • Account for pipeline stages, data dependencies, and timing constraints. • Use tools like Verilog, system-Verilog, or specialized simulation environments to achieve cycle-accurate modeling. 4. Performance Analysis and Optimization: • Profile the NPU model to identify bottlenecks and areas for improvement. • Propose and implement optimizations to enhance performance and reduce latency. • Collaborate with software teams to fine-tune the NPU's behavior. 5. Verification and Validation: • Create testbenches and test vectors to validate both the bit-true and cycle-accurate models. • Conduct functional and performance testing to ensure correctness and compliance with specifications. • Debug and resolve any discrepancies between the models and the actual NPU. 6. Documentation and Communication: • Document the NPU architecture, design decisions, and implementation details. • Present findings, progress, and challenges to stakeholders and management. • Collaborate with software engineers, firmware developers, and system architects. Qualifications: • Master's or Ph.D. degree in Electrical Engineering, Computer Science, or a related field. • Minimum of 3 years of experience in NPU architecture design and implementation. • Proficiency in C/C++/Verilog/System-Verilog programming for hardware modeling. • Familiarity with systolic arrays, matrix multiplication, and neural network accelerators. • Knowledge of bit-true modeling, fixed-point arithmetic, and floating-point arithmetic. • Experience with verification tools and simulation environments. • Strong analytical and problem-solving skills. • Excellent communication and teamwork abilities. • Attention to detail and commitment to quality. If you are passionate about NPU architecture, hardware modeling, and want to be part of a team driving innovation, we encourage you to apply. Join us in shaping the future of AI!