「FPGA資深/主任工程師_5G(台北/新竹)」的相似工作

This vacancy is open for talent pool collection. We will contact you if we have proper vacancies that fit with your profile. Job Mission Represent manufacturing and act as gatekeeper from manufacturing to D&E function Add value in overall manufacturing processes such as forming, machining, joining, and assembling Job Description Contribute to the solution of faults and takes the necessary initiatives and practical decisions to ensure zero repeat Identify gaps and drive assigned process improvement projects and successful delivery Initiate and drive new procedure changes and projects Develop and maintain networks across several functional stakeholders Prioritize works and projects based on business situation Transfer knowledge and train colleagues on existing and newly introduced products Education Master degree in technical domain (e.g. electrical engineering, mechanical engineering, mechatronics) Experience 3-5 years working experience in design engineering Personal skills Show responsibility for the result of work Show proactive attitude and willing to take initiative Drive for continuous improvement Able to think outside of standard processes Able to work independently Able to co-work with different functional stakeholders Able to demonstrate leadership skills Able to work in a multi-disciplinary team within a high tech(proto) environment Able to think and act within general policies across department levels Diversity and inclusion ASML is an Equal Opportunity Employer that values and respects the importance of a diverse and inclusive workforce. It is the policy of the company to recruit, hire, train and promote persons in all job titles without regard to race, color, religion, sex, age, national origin, veteran status, disability, sexual orientation, or gender identity. We recognize that diversity and inclusion is a driving force in the success of our company. Need to know more about applying for a job at ASML? Read our frequently asked questions.

Theoretical and practical experience in the following fields: 1. Experience in Wireless Communication Layer 1 Specification on LTE/NR 2. Experience in Automatic Gain control (AGC), Automatic frequency control (AFC), timing error adjustment, and DPD (Digital Pre-Distortion)/CFR (Crest Factor Reduction) 3. Familiarity with Digital Signal Processing(MIMO, Equalizer, Modulation, and OFDM System Simulation…. ,etc) 4. Familiarity with Digital filter design (IIR, FIR, multirate filter, Upsampling/Downsampling, Interpolator/Decimator, Resampling) 5. Development experience is not restricted, but candidates should meet at least 2 out of the 4 criteria listed above. Nice-to-have skills：  Experience in Software development on MCPS/Memory optimization & Multi-cores/Multi-threads scheduling is preferred  Experience in Layer 2 to Layer 1 interface design or implementation is preferred.  Experience in embedded system/RTOS, kernel/CPU architecture is preferred  Experience in driver/ tool chain development is preferred

1. 支援計畫功能與系統驗證與除錯。 2. 規劃及協調驗證資源、項目及時程。 3. 與Hardware engineer 溝通設計FPGA硬體架構規劃 4. 與Software engineer 溝通設計FPGA 控制介面 5. SoC FPGA系統整合。 6. 演算法之RTL實現或IP整合、獨立撰寫 Testbench & Debug FPGA電路 7.高速介面(HDMI/eDP/3G-SDI/12G-SDI)、DDR、I2C、UART、SPI等介面整合應用 8. 具醫療影像及色彩處理開發

1. Verilog or VHDL程式經驗 2. 應用FPGA之功能設計

Overview We are seeking a highly skilled FPGA Engineer to architect and implement high-performance digital logic for next-generation camera platforms. This role is pivotal in enabling real-time video processing and efficient sensor integration. Key Responsibilities Design & Implement Camera Interfaces: Develop FPGA logic to handle high-speed camera data streams (e.g., MIPI, LVDS, CSI). Real-Time Image Processing: Integrate or design FPGA IP cores for image signal processing, filtering, and feature extraction. Sensor Synchronization: Ensure precise timing between multiple camera modules and other sensor inputs. Latency Optimization: Optimize FPGA architectures for low-latency video capture and data throughput. Verification & Testing: Create simulation testbenches and perform hardware-in-the-loop testing for camera pipelines. Collaboration: Work closely with camera hardware and system integration teams to define requirements and validate performance.

1. CPLD/FPGA 經驗 Verilog、VHDL 程式編輯經驗 2. X86 ARM 架構 CPLD 設計經驗 3. 硬體設計架構系統規劃 4. 獨立專案作業能力佳 5. Module code 組織編輯能力 *歡迎對verilog coding有興趣者投遞，公司將依學經歷、能力核敘

1.Work with Hardware, BIOS ,BMC, and Firmware team for CPLD design, validation, and maintenance 2.Develop Server production power on sequence control logic by CPLD / FPGA 3.Implement new technology and design concept in CPLD / FPGA Design test plan, development specification, and issue tracking.

1. 主動式電子掃描陣列 (相控陣列) 雷達系統之數位控制。 2. 熟悉Verilog與FPGA開發流程，了解High-Level Synthesis開發技術。 3. 具有實作數位訊號處理與數位架構設計於FPGA之經驗。

1.客戶FPGA and SoC 技術相關問題處理 2.FPGA and SoC 設計技巧教育訓練 3.Xilinx 產品推廣

【工作內容】 1. 數位電路邏輯控制程式設計 2. 基本通訊界面控制 (UART/I2C/SPGIO/SPI) 3. CPLD規格評估 4. CPLD規格書規劃、撰寫、維護 5. Verilog/VHDL模擬除錯設計 6. CPLD測試、除錯、驗證及最佳化 7. 維護現有CPLD專案 【其他條件&加分項目】 1. 熟悉 Verilog, 2. 若具有 Altera Quartus II, Lattice Diamond , Modelsim能力佳 3. 具有開創性及解決問題的能力 4. 客戶導向及良好溝通技巧 5. 具備推動團隊完成任務的能力 6. 流程管理能力

1. 熟Verilog及C/C++語言設計。 2. 規劃執行產品韌體之撰寫。 3. 執行、協助或配合韌體新技術之研發、導入。 4. 執行產品韌體測試。

A. 負責高階投影機FPGA開發 B. 承接 FPGA (XILINX/ALTERA) 設計 C. 數位電路設計、驗證與模擬 D. 影像系統或數位影像處理演算法設計與實現

[工作內容] • 研究建立Linux/X86/ARM-based環境模擬器，可類比系統串接多種硬體裝置。 • 協助產品安全測試執行，讓模糊測試(fuzzer)執行時可以在一個模擬的硬體環境進行相關評估。

FPGA 運用設計

1. FPGA加速應用系統整合開發與驗證 2. IP開發/驗證/整合 3. 產品除錯與分析支援

我們正在尋找對 FPGA 設計有熱情的初階工程師與資深工程師，負責基於 Xilinx FPGA 平台的邏輯設計與實作。 本職位也需要具備基本的 C/C++ 程式設計能力，進行嵌入式控制、軟硬體整合及模擬驗證。 [工作職責] - 使用 Vivado / Vitis 開發 Xilinx FPGA（Zynq/Artix/Kintex/Virtex 等）之 RTL 模組。 - 撰寫 RTL（Verilog/VHDL）實現高速資料路徑、介面邏輯與控制模組。 - 撰寫 Testbench 進行模擬驗證。 - 利用 C/C++ 開發與 FPGA 互動的測試程式或 ARM 嵌入式軟體。 - 協助進行軟硬體整合、除錯與效能優化。 [必備條件] - 電機、電子、資工、資電等相關科系碩士學位。 - 熟悉 FPGA 設計流程與工具（Vivado、ISE、Quartus 等）。 - 熟悉 Verilog 語言基本語法。 - 具備 C/C++ 程式設計與 Debug 技巧。 - 具備 ARM 嵌入式系統及硬體控制相關開發經驗。 - 具備基礎的數位電路與硬體架構知識。 [加分條件] - 具備 Zynq SoC (ARM + PL) 系統整合經驗。 - 熟悉 AXI Bus、DMA、DDR、SPI、I2C 等介面協定。 - 熟悉高階合成（HLS）。 - 熟悉 Linux 系統及 MCU 系統開發經驗。

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About us: VICI Holdings' Hardware team is seeking a skilled FPGA Engineer to join our dynamic group. In this role, you will be pivotal in advancing our trading systems, contributing to the development and enhancement of cutting-edge technologies. We boast the leading software development team in Taiwan and possess FPGA design technology in parallel with wall street trading firms. This expertise enables us to build low-latency, fully automated trading systems. Our trading strategies cover stocks, futures, and derivatives, achieving a daily global trading volume in the hundreds of millions dollars. Roles/ Responsibilities: • High speed IP interface design (such as PCIE gen 3, 4 / Ethernet, DDR etc.) • In charge of FPGA design/ implementation/simulation. • Transmission protocol layer development. • Optimizing hardware for latency. • Proficiency with Xilinx design environment. Candidate Requirements: • BS/MS degree above from EE, CE with 2+ years of relevant work experience • Experience in high-speed interface design or knowledge in PCIE/ Ethernet/MIPI/DDR design or implementation is a plus • Experience using System Verilog and at least two prior RTL design is a required. • Demonstrated ability to tackle complex design challenges and implement effective solutions Other Requirements: • High self-motivated individual with good communication skill. • English level – working level proficiency is a plus. Interview Process: • Resume selection ->Coding Test -> AI Interview (Online) -> F2F Interview -> HR Manager

Digital IC design engineer - Familiar with Verilog RTL coding - Familiar with digital design flow (pre-layout simulation, timing constraint, synthesis, post-layout simulation) - Will be working on high speed Serdes IPs - Experience or interest in all-digital PLLs or clock-data recovery circuits is a big plus

產品領域: 影像, CPO及衛星光通訊產品使用之 FPGA。 工作內容: 1. 熟練使用Verilog及VHDL 2. 熟悉Combine/Sequential Logic、FSM、pipeline、clock domain crossing (CDC)、reset strategy 等應用 3. 自動化設備嵌入式系統開發 4. 研發設計FPGA-Based Video/Camera 應用 5. 熟悉FPGA系統開發、RTL Coding、Altera Quartus II或Xilinx Vivado 6. 協助驗證FPGA電路(Schematic) 7. 具備基礎MS Windows Programming能力者佳 8. 熟悉I2C、UART、I2S 等protocol 者佳