「通訊數位IC設計工程師(I15)」的相似工作

【產品線描述】 Evolution Video Display 新興顯示器開發： 1. Gaming monitor controller for LCD, OLED and Mini-LED. 專業電競螢幕，極致沉浸競界曲面螢幕，遊戲體驗身歷其境 2. Public display controller for LCD and Micro/Mini-LED. 大型商用顯示器，極窄邊框拼接電視牆，電子白板 3. Electronic Vehicle Display Controller. AR/2D HUD(抬頭顯示器)，車用高速顯示介面 4. Advanced Projector Controller. 低延遲的遊戲投影機、短焦投影機、浮空影像顯示器 【工作說明】 電路硬體設計與開發 1. 顯示器或車用顯示系統架構開發 (System Architecture Development) (a) CPU/MCU架構整合 (b) SoC system bus 與 bridge架構規劃設計 Familiar with AXI/AHB/APB/Arbiter (c) DDR memory controller 2. 高速數位介面 High-Speed I/F (a) HDMI TX/RX link layer (HDMI1.4/2.0/2.1) (b) DP TX/RX link layer (DP1.4/2.0) (c) MIPI RX link layer (d) Vx1 link layer (e) USB Type-C controller 3. Picture Quality(PQ) (a) 視訊影像處理,色彩轉換演算法開發有興趣或具經驗 (b) HDR10+, Dobly Vision 4. FPGA 平台設計 5. APR flow (a) Synthesis/STA (b) DFT (c) Low-power flow (d) APR co-work 【必要條件】(熟悉或有相關經驗) 1. 顯示器或車用顯示 CPU/MCU/DDR controller/bus bridge相關經驗 2. 高速數位介面 High-Speed I/F HDMI TX/RX / DP TX/RX / Vx1 相關經驗 3. Picture Quality(PQ) 視訊影像處理經驗 車用相關IC 設計經驗 4. SOC 整合經驗

1.根據通訊演算法，撰寫RTL code (Verilog, VHDL) 2.數位電路設計。 3.承辦及參與委託給業界或學界之研發案。

1. 主動式電子掃描陣列 (相控陣列) 雷達系統之數位控制。 2. 熟悉Verilog與FPGA開發流程，了解High-Level Synthesis開發技術。 3. 具有實作數位訊號處理與數位架構設計於FPGA之經驗。

【產品線描述】 1. AMOLED, AR, VR, TDDI等面板驅動IC與觸控IC設計 2. 頂級系統廠ASIC產品合作開發 【工作說明】 1. 高速介面設計 2. 記憶體控制單元設計 3. 面板時序電路設計 4. 面板顯示優化控制單元設計 【必要條件】 1. MS degree in EE fields 2. Good at digital IC front-end design flow such as Verilog RTL design, Synopsys Design compiler, LEC, PrimeTime STA and FPGA 3. Must be a good team player with strong desire to succeed.

【產品線描述】 Evolution Video Display 新興顯示器開發： 1. Gaming monitor controller for LCD, OLED and Mini-LED. 專業電競螢幕，極致沉浸競界曲面螢幕，遊戲體驗身歷其境 2. Public display controller for LCD and Micro/Mini-LED. 大型商用顯示器，極窄邊框拼接電視牆，電子白板 3. Electronic Vehicle Display Controller. AR/2D HUD(抬頭顯示器)，車用高速顯示介面 4. Advanced Projector Controller. 低延遲的遊戲投影機、短焦投影機、浮空影像顯示器 【工作說明】 1. Gaming 高階顯示器及戶外大型顯示看板 SoC 控制IC 設計, 驗證及量產測試 2. Video/Image/Color 相關演算法開發 3. 高階製程 whole chip 及 IP 整合, DFT 及 low power 設計流程及驗證 【必要條件】(符合下列一或多項者) 1. SoC IC 設計流程實務經驗 2. Whole chip 整合, STA timing 分析, 以及 APR co-work 經驗 3. CPU 架構與整合經驗 4. SoC internal bus 及 bridge 架構規劃及整合經驗 5. 高速數位介面 HDMI,DP, MHL,Vby1 等controller 電路開發經驗 6. 加解密(例如: HDCP 1.x, HDCP 2.2, ...) 硬體電路設計經驗 7. SDR/DDR Memory Controller 設計經驗 8. USB Type C controller 設計經驗 9. 對視訊影像處理,色彩轉換演算法開發有興趣或具經驗

1. 光通訊產品相關高速介面數位設計 (112G PAM4 SerDes) 2. 依據系統規格, 執行架構設計以及撰寫硬體描述語言 (RTL) 3. 具有高速介面, 低功耗, 以及D/A混合電路設計經驗者尤佳

1. Architecture design and RTL implementation of Automotive/Smartphone chipset 2. SoC system power and performance analysis 3. SoC system bus and memory subsystem design, integration, and modeling 4. SoC low power design, integration, and modeling 5. SoC functional safety analysis, design, integration, and modeling 6. SoC cyber security analysis, design, integration, and modeling

The successful candidate will work with team members and apply his/her design techniques to work on different phases of complex logic design for ASIC/SOC project. The role will include working on the following tasks from time to time: HDL coding, documentation, RTL quality check, cooperate with back-end engineer etc. 【Key Responsibilities】 - Responsible for front-end digital logic design in ASIC/SOC projects. - Perform HDL coding (Verilog/SystemVerilog). - Prepare and maintain design documentation (specifications and design documents). - Conduct RTL quality checks (Lint, CDC, power analysis, etc.). - Collaborate with Backend/Physical Design engineers to achieve timing closure. 【Core Requirements】 - Education/Experience: Master’s degree with ≥ 2 years, or Bachelor’s degree with ≥ 3 years of digital ASIC/SOC design experience. - RTL Design: Proficient in RTL coding using Verilog/SystemVerilog or VHDL. - TO / Front-End Flow: Familiar with front-end design flow, including synthesis, Lint, CDC, and STA. - EDA Tools: Experience with tools such as Lint, CDC check, and PrimeTime PX (power analysis). - Documentation: Ability to write design specifications and technical documents. - Collaboration: Work closely with the Design Verification (DV) team on IP verification. 【Preferred Qualifications】 - Familiarity with CPU architectures (x86/ARM/8051). - Knowledge of AMBA bus protocols (AXI/AHB/APB). - Understanding of PCIe protocol.digital IP/SOC design verification.

(a) 負責Tcon IC開發 (b) 負責數位影像處理IP開發 (C) 1.整合使用 FPGA IP，具模擬驗證以達功能的需求 2.系統驗證項目的規劃及系統整合與測試 3.開發、撰寫及驗證 Verilog code (D) 1.使用System Verilog、UVM驗證數位IP 2.依據規格擬定測試計畫並建立隨機測試向量 3.與Design Team密切合作，提高function/code test coverage

Responsible for digital IP coding and micro-architecture design of low-power, high-performance LLM inference accelerators. Drive mapping of lightweight frameworks such as llama.cpp onto NPU, plan compute/memory subsystems, and optimize quantization & KV-cache for production-ready LLM SoCs. Write RTL specs and guide DV plans and P&R convergence for PPA targets. 1. 研讀規格。 2. IC數位邏輯線線路的研發設計。 3. IC數位邏輯線路模擬與合成。 4. FPGA的合成規劃與測試驗證。 5. IC的靜態時序分析 (Static Timing Analysis)。 6. IC佈局後的線路模擬。 7. 撰寫IC規格設計書。 8. IC的除錯與工程變更修改。 9. 協助系統應用部門的進行IC驗證版的規劃。

歡迎2026年畢業並正在找尋研發替代役的同學申請! 職位選擇: Direction 1: Physical Design Engineer Direction 2: ASIC Physical Design Engineer Direction 3: DFX Engineer Direction 4: CAD Tools Development Engineer Direction 5: Design Verification Engineer What you’ll be doing: Key Domains: • Physical and ASIC Design Implementation • Backend and Layout Optimization • Design-for-Excellence (DFX: Test, Manufacturability, Debug) • Development of CAD/EDA Automation Tools • Functional and Formal Design Verification What we need to see: • MS degree from EE/CS or related majors from a prestigious university. • Good knowledge in digital circuit design. • Experience in using Verilog HDL. • Experience in various EDA tools. • Fluent in English reading and writing. • Self-motivated, good team player. Ways to stand out from the crowd: • Proven ability to work independently as well as in a multi-disciplinary group environment • Good command of C/C++ or Verilog programming language. • Familiar with Perl/Python/Tcl/Shell scripting 應徵方式: 請提供以下資料： • 英文個人履歷 • 學士+碩士成績單 (中英文皆可) 提交申請: 請將上述資料投遞至104，符合資格者將會收到進一步的聯繫通知。

我們專注於3D影像立體雙目視覺技術 產品應用於3D 影像辨識、360 度環景拍照、攝影或AR 與VR 職務內容： ★ USB2.0/3.1或 MIPI 介面之2D/ 3D 影像處理與壓縮之 IC 開發 ★ 影像處理與壓縮相關數位 IP暨產品之開發設計、測試、驗證 條件要求： 1. 對IP Verification, System Verification 有興趣 2. 熟Verilog coding 與 ASIC design Flow 與 Timing Closure 3. 或有 SoC IC 開發經驗 4. 對開發人工智慧((AI) 晶片與邊緣運算有興趣者

About us: VICI Holdings' Hardware team is seeking a skilled FPGA Engineer to join our dynamic group. In this role, you will be pivotal in advancing our trading systems, contributing to the development and enhancement of cutting-edge technologies. We boast the leading software development team in Taiwan and possess FPGA design technology in parallel with wall street trading firms. This expertise enables us to build low-latency, fully automated trading systems. Our trading strategies cover stocks, futures, and derivatives, achieving a daily global trading volume in the hundreds of millions dollars. Roles/ Responsibilities: • High speed IP interface design (such as PCIE gen 3, 4 / Ethernet, DDR etc.) • In charge of FPGA design/ implementation/simulation. • Transmission protocol layer development. • Optimizing hardware for latency. • Proficiency with Xilinx design environment. Candidate Requirements: • BS/MS degree above from EE, CE with 2+ years of relevant work experience • Experience in high-speed interface design or knowledge in PCIE/ Ethernet/MIPI/DDR design or implementation is a plus • Experience using System Verilog and at least two prior RTL design is a required. • Demonstrated ability to tackle complex design challenges and implement effective solutions Other Requirements: • High self-motivated individual with good communication skill. • English level – working level proficiency is a plus. Interview Process: • Resume selection ->Coding Test -> AI Interview (Online) -> F2F Interview -> HR Manager

Design CPU functional units. Responsibilities  Defining micro-architecture of the functional units  Writing RTL codes of the functional units  Writing documents of the function units  Working with cross-division teams to resolve functional, performance, power, and frequency issues related to the functional units Qualifications  Available to start work three months after being hired.  3+ years of recent experience with Verilog logic design  Knows CPU micro-architecture, e.g. instructions, pipeline, caches, MMU  Knows power consumption of digital circuits  Good communicator in verbal and writing in English

【產品範疇】 MOBILE(手持裝置)驅動晶片 【工作內容】 LCD driver(含OLED) Timing Control數位電路的研發設計與驗證 【需求條件】 1.熟悉HDL coding, simulation, synthesis, and STA flow，有量產經驗尤佳 2.熟悉LCD driver(或OLED)規格，具有相關工作經驗尤佳 3.熟悉Timing Control(Global Timing or SRC control timing or GIP timing)數位電路設計，有相關開發經驗者尤佳

1. IDC觸控數位電路設計 (AFE) 2. SOC周邊數位電路設計 3. SOC數位電路整合

1. SerDes CTRL IP RTL 開發與維護 (例如LPDDR､UFS､NAND Controller...) 2. 設計驗證 3. FPGA相關設計與實作 以上工作依個人意願酌情分配

[job description] Wolley is seeking candidates for a digital design engineer position. You will join an experienced team designing next-generation memory, storage controllers, and high-speed interface standard. You will also contribute to design concept discussion, architecture definition, as well as design implementation. ‧ Architecture design and RTL implementation ‧ System bus and related peripheral designs ‧ SoC and emulation platform design ‧ SoC system performance analysis [Requirement] 1. Bachelor's or Master's degree in Electrical Engineering or related fields 2. Familiar with RTL design, SystemVerilog, front-end design flow 3. The following working knowledge is desired: * Python programming * TCL scripting * Universal Verification Methodology (UVM) * Low power design and analysis

1. ARM CPU design physical implementation 2. ARM CPU power and timing sign off 3. Physical design flow enhancement for high-speed CPU

此專區為符合2026年研發替代役及預聘者投遞，如非研替/預聘身分者，歡迎投遞創未來其他職缺！ ##職務類別 1. 數位IP設計工程師 2. 數位前端整合工程師 3. 數位電路FPGA整合設計工程師 4. 韌體工程師 5. 數位訊號處理演算法工程師 ##工作內容 1. 應用於雷達、數位感測、衛星通訊之訊號處理數位IP設計。 2. 數位IP架構設計與實作。 3. FPGA數位系統開發與整合合成優化。 4. 微波、類比電路控制、校準設計韌體實作 。 ##技能需求 1. 具數位訊號處理經驗。 2. 具備數位電路設計經驗。 3. 熟悉Verilog/VHDL、TCL等。 ##應徵資格 1. 2026年畢業之應屆碩/博畢業生。 2. 研究所以上電子/電機/電信/通訊相關科系畢業。 3. 欲應徵者請檢附成績單、論文摘要。