「網通 FPGA/CPLD研發工程師_新竹_00000」的相似工作

1.客戶FPGA and SoC 技術相關問題處理 2.FPGA and SoC 設計技巧教育訓練 3.Xilinx 產品推廣

1. 負責 FPGA 功能驗證、程式開發、測試、除錯及維護 2. 撰寫 Testbench 進行模擬驗證 3. 具 I2C、SPI 通訊介面運作經驗者 4. 熟悉 Xilinx RFSoc 架構與設計 5. 熟悉 Linux Driver 實作經驗

1. 支援計畫功能與系統驗證與除錯。 2. 規劃及協調驗證資源、項目及時程。 3. 與Hardware engineer 溝通設計FPGA硬體架構規劃 4. 與Software engineer 溝通設計FPGA 控制介面 5. SoC FPGA系統整合。 6. 演算法之RTL實現或IP整合、獨立撰寫 Testbench & Debug FPGA電路 7.高速介面(HDMI/eDP/3G-SDI/12G-SDI)、DDR、I2C、UART、SPI等介面整合應用 8. 具醫療影像及色彩處理開發

1. 伺服器產品之機構設計及文件資料維護 2. 3D和2D圖檔新增及維護 3. 機構件模具DFM檢討及試模 4. 機構件之GPM及樣品承認 5. 試產、組裝驗證、量產之機構設計確認及分析 6. PCB Design with EE & Layout

工作敘述： 此職缺為扮演半導體無晶圓製造商與供應商及內部量率工程單位之間的Tier 1 支援。 1. 晶圓代工廠資料傳送流程與資料正確性檢核 (MES/ERP/Shipment透過雲端地端設備傳輸) 以及問題排查。 2. 半導體封裝測試廠資料傳送與資料正確性檢核與問題排查 (Data pipeline的異常管理)。 3. 提供Tier 1層級技術支援 (資料庫以及雲端地端 Data pipeline ETL相關問題)必要時升級問題至Tier 2層級尋求支援。 4. 資料自動化流程成優化 (含程式[Script]撰寫等)。 5. 其他主管交辦事項。 所需技能： 1. SQL 基本語法使用 2. Unix基本指令 (Command line) 3. 基礎雲端與ERP知識 4. Python /Java 或任一程式設計基本概念 5. 基本商用英文，多益600分以上 6. 熟悉 ticket 管理系統 (例如: Jira) 加分項： 1. 製造業背景，對電子業生產流程有基本了解 2. 能細心排查資訊部門的問題並與相關單位提出解決對策 3. 能以基本英文開會 學歷：專科以上 科系限制：資訊工程(管理)/工業工程(管理)

Responsibilities: • Develop integrated verification environment. • Verify designs with system verilog and system verilog assertion. • Build, maintain and upgrade testbenches and their components using UVM-based methods. • Check functional coverage and code coverage • Create controlled random testcases. Pre-debug and provide debug reports. • Scripting experience using scripting languages like Perl and Python.

1. 主動式電子掃描陣列 (相控陣列) 雷達系統之數位控制。 2. 熟悉Verilog與FPGA開發流程，了解High-Level Synthesis開發技術。 3. 具有實作數位訊號處理與數位架構設計於FPGA之經驗。

1. Architecture design and RTL implementation of Automotive/Smartphone chipset 2. SoC system power and performance analysis 3. SoC system bus and memory subsystem design, integration, and modeling 4. SoC low power design, integration, and modeling 5. SoC functional safety analysis, design, integration, and modeling 6. SoC cyber security analysis, design, integration, and modeling

Develop and maintain environment for SOC pre-silicon verification of: • RTL and netlist simulation • CRV for system fabric • Power-aware simulation • Formal CC and FPV • System level verification with SVA

Main JD: 1. System firmware and diagnostic development for EVT/DVT/PVT (using C/C++)or Automated test program development for EVT/DVT/PVT (using Python) 2. Co-work with cross-functional teams on projects 3. Communicate with customers in English Secondary JD: 1. Assist cross-functional teams on projects to resolve software-related issues 2. Develop some tools to assist EVT/DVT/PVT

1.具FPGA平台開發相關經驗 2.熟Verilog 3.熟顯示器TCON/Driver驅動原理者佳 4.能獨立建立FPGA開發環境平台 5.有數位邏輯IC開發經驗者佳

(1) FPGA軟硬體開發 (2) Verilog程式開發 (3) 軟硬體除錯

1. 參與公司數位後段設計 之產品開發 2. 熟悉與維護 並參與 新流程之開發

【工作內容】 1. 數位電路邏輯控制程式設計 2. 基本通訊界面控制 (UART/I2C/SPGIO/SPI) 3. CPLD規格評估 4. CPLD規格書規劃、撰寫、維護 5. Verilog/VHDL模擬除錯設計 6. CPLD測試、除錯、驗證及最佳化 7. 維護現有CPLD專案 【其他條件&加分項目】 1. 熟悉 Verilog, 2. 若具有 Altera Quartus II, Lattice Diamond , Modelsim能力佳 3. 具有開創性及解決問題的能力 4. 客戶導向及良好溝通技巧 5. 具備推動團隊完成任務的能力 6. 流程管理能力

The successful candidate will work with team members and apply his/her design techniques to work on different phases of complex logic design for ASIC/SOC project. The role will include working on the following tasks from time to time: HDL coding, documentation, RTL quality check, cooperate with back-end engineer etc. 【Key Responsibilities】 - Responsible for front-end digital logic design in ASIC/SOC projects. - Perform HDL coding (Verilog/SystemVerilog). - Prepare and maintain design documentation (specifications and design documents). - Conduct RTL quality checks (Lint, CDC, power analysis, etc.). - Collaborate with Backend/Physical Design engineers to achieve timing closure. 【Core Requirements】 - Education/Experience: Master’s degree with ≥ 2 years, or Bachelor’s degree with ≥ 3 years of digital ASIC/SOC design experience. - RTL Design: Proficient in RTL coding using Verilog/SystemVerilog or VHDL. - TO / Front-End Flow: Familiar with front-end design flow, including synthesis, Lint, CDC, and STA. - EDA Tools: Experience with tools such as Lint, CDC check, and PrimeTime PX (power analysis). - Documentation: Ability to write design specifications and technical documents. - Collaboration: Work closely with the Design Verification (DV) team on IP verification. 【Preferred Qualifications】 - Familiarity with CPU architectures (x86/ARM/8051). - Knowledge of AMBA bus protocols (AXI/AHB/APB). - Understanding of PCIe protocol.digital IP/SOC design verification.

1. Design verification with SystemVerilog/UVM, C/C++ 2. Integration test environment with VIP 3. Develop checker and scoreboard. 4. Verify design with SystemVerilog assertion. 5. Test plan for a verification task. [Requirement] 1. Familiar with SystemVerilog HDL, OOP, Python, TCL, and shell programming. 2. Better to have SoC design and bus concept.

## 職務說明 - 應用於無人機雷達系統 - 數位IP架構設計與實作。 - 透過MATLAB/C++協助數位IP驗證 - 透過FPGA整合與驗證。 ## 技能要求 - 具備數位訊號處理經驗 - 具備數位電路設計經驗 - 程式語言必要：Verilog/VHDL, TCL, ##加分條件： - 具備雷達/通訊訊號處理、數位設計架構 - 具備RF/Analog 知識與RF/Analog校準設計 - 程式語言: MATLAB, python, c, c++, Chisel3

(1) DRAM電路設計與模擬驗證 (2) 具備DRAM ROW/COLUMN/CONTROL/DC/DLL任一或更多電路設計經驗者佳 (3) 具備verilog經驗者尤佳 (4) 了解基本UNIX操作，具備AWK等Programing能力者尤佳 (5) 具備電機電子資訊物理相關背景，無工作經驗可

1. 主FPGA與CPLD專案開發與維護 2. 熟RTL coding, 具Xilinx ISE/Vivado或Altera Quartus II專案設計經驗 3. 能與軟,韌,硬體等相關部門co-work 4. 具Xilinx PCIe 與 MIG DDR3/4系統整合經驗者佳

DRAM數位邏輯電路設計 『具工作經驗者，薪資另議』