「Analog IC technical manager」的相似工作

Job Description: As a team member of analog product business group, this role will support Analog IC circuit design of mixed-signal ICs, such as sensors, motor drivers, data converters. Key Responsibilities: 1. Co-work with talented design teams to develop high performance sensor related integrated circuits and products, such as Hall effect sensor, temperature sensor. 2. Contribute to chip architecture and circuit design decisions 3. Collaborate with validation, product engineering and test engineering teams to enable successful transfer to production 4. Also, will be responsible for circuit requirements definition, design, simulation and analysis, layout/test support, documentation and customer support for sensor applications. Qualifications: 1. Demonstrate strong analytical and problem-solving skills 2. Strong time management skills that enable on-time project delivery 3. In depth working experience with Cadence composer and Virtuoso, Spectre, HSpice and mixed-signal design flow. 4. Experience in lab measurement and equipment. 5. Self-starter. Passionate about creative work. Good communication skills and team player. Able to take the initiative and drive for results.

振生半導體股份有限公司 (Jmem tek) 專注於半導體相關矽智財，提供設計服務與硬體資安專利，保護硬體資訊安全。如果您希望參與一個充滿潛力和創造力的環境，歡迎您加入我們的團隊。 工作內容： 1.負責混合訊號電路設計與模擬（包含 ADC、DAC、PLL 等電路）。 2.設計與開發電源管理電路（PMIC），包含 Charge Pump、LDO、Bandgap 參考源等模組。 3.開發高壓電源（High Power Domain）與核心電壓域（Core Voltage Domain）間的介面與穩壓電路。 4.撰寫模擬驗證計畫，執行電路模擬（Transient, AC, Noise, Corner, Monte Carlo 等）並分析結果。 5.配合數位 IC 工程師完成 Mixed-Signal Top-level 整合與 SoC 系統整合工作。 6.參與實體設計流程，完成晶片整合、驗證與 Tape-out。 7.撰寫設計規格書、模擬報告與設計文件，確保開發流程完整性與可維護性。 我們期望您具備的條件： 1.電子、電機相關科系碩士以上學歷，具備類比或混合訊號設計背景。 2.具備 3 年以上類比 IC 設計實務經驗。 3.熟悉常用類比模組設計（如 OTA、Bandgap、Comparator、Reference、Voltage Regulator 等）。 4.熟悉混合訊號模擬與驗證工具（如 Cadence Spectre、HSPICE、AMS flow）。 5.熟悉 ESD/LVTS、Latch-up、Layout Matching 基本設計原則。 6.具備先進製程經驗（如 TSMC 16nm、12nm、7nm）者佳。 7.具備晶片整合與量產經驗者尤佳。 8.具備良好溝通能力，能與 Layout、數位設計與測試工程師有效合作。 相關報導： 量子電腦資安攻防戰！振生半導體首創PUF+PQC市場唯一最佳解方https://udn.com/news/story/7240/7917935 EE TIMES 報導：振生半導體引領IC安全創新 https://www.eettaiwan.com/videos/jmem-technology-leads-ic-security-innovation/ 2024台灣新創世界杯「振生半導體奪冠」　10月赴美爭百萬美元投資款 https://finance.ettoday.net/news/2786606 DIGITIMES Asia報導：Chip startup JMEM TEK safeguards data security with hardware-software solution https://www.digitimes.com/news/a20221223VL202.html

Digital IC design engineer - Familiar with Verilog RTL coding - Familiar with digital design flow (pre-layout simulation, timing constraint, synthesis, post-layout simulation) - Will be working on high speed Serdes IPs - Experience or interest in all-digital PLLs or clock-data recovery circuits is a big plus

We are seeking a skilled Analog IC Design Engineer with expertise in MIPI TX/ PLL design and sensor readout circuits. The ideal candidate will possess a strong foundation in analog design and a passion for developing cutting-edge solutions in a collaborative environment. 1.Design and implement MIPI TX and PLL circuits for high-speed data transmission. 2.Develop charge pump and LDO (Low Dropout Regulator) circuits to ensure efficient power management. 3.Design and optimize oscillator (OSC) circuits for precise timing applications. 4.Create sensor readout circuits, including CDS (Correlated Double Sampling), TDC (Time-to-Digital Converter), ramp circuits, DAC (Digital-to-Analog Converter), and comparators. 5.Collaborate with system engineers to define specifications and ensure alignment with overall project requirements. 6.Perform circuit simulations and analyses using tools such as Cadence, Spectre, or HSPICE. 7.Conduct design verification and validation through prototyping and testing. 8.Optimize designs for performance, power efficiency, and reliability. 9.Participate in design reviews and contribute to project documentation. 10.Provide support during the layout and fabrication process. Preferred Qualifications: 1.Familiarity with IP design principles. 2.Experience with mixed-signal circuits. 3.Knowledge of low-noise and high-speed design techniques.

Job desicription: Our Design Team specializes in the challenging field of Non-Volatile Memory (NVM) IC circuit design. We are actively seeking an experienced Analog Circuit Design Engineer to contribute to our cutting-edge developments in embedded NVM solutions and surrounding circuitry. As a key member of our team, you will be responsible for the design, verification, and debugging of essential analog building blocks like Bandgap references, LDOs, and Charge Pumps. A significant part of your role will involve designing critical memory peripheral circuits for NVM IP and test chips, including Array interfaces, Decoding logic, and Sense Amplifiers. Your responsibilities will span the design lifecycle, from contributing to IP specifications and core circuit design to ensuring performance through layout optimization and comprehensive corner simulations of NVM IPs. We are looking for candidates with proven expertise in analog circuit design, ideally with prior experience in embedded memory or NVM technologies. If you are an experienced analog designer eager to tackle complex challenges in non-volatile memory, we encourage you to apply and help shape the future of memory technology.

具備1~4之中1種以上的設計經驗。 1. 放大器應用電路; band-gap, op-amp, filter, etc. 2. 電源類比電路: DCDC, LDO, charge-pump, etc. 3. 信號處理電路: SAR ADC, sigma-delta ADC, DAC, etc. 4. 時脈產生電路: PLL, DLL, frequency synthesizer, etc.

記憶體power system 設計 『具工作經驗者，薪資另議』

1.Analog front-end design 2.ADC design(Pipelined, SAR, Delta-sigma ADCs) 3.Switched-capacitor circuit design 4. Low EMI techniques 5. Mixed-signal system integration & modeling 6.負責layout floorplan規劃，與layout工程師合作完成相關驗證

1.Design and maintain analog circuits 2.Survey and maintain design processes 3.Survey and maintain design tools and flow 4.Help training junior engineers 5.Debugging and measuring chip

1. SAR ADC / Current steering DAC/ SDM ADC/ DAC related 2. Analog Baseband related 3. 據有類比整合相關經驗佳

Responsible for developing custom IP for SoC design from specification definition, circuit design to testing, and familiar with component and process characteristics.

(1) DRAM電路設計與模擬驗證 (2) 具備DRAM ROW/COLUMN/CONTROL/DC/DLL任一或更多電路設計經驗者佳 (3) 具備verilog經驗者尤佳 (4) 了解基本UNIX操作，具備AWK等Programing能力者尤佳 (5) 具備電機電子資訊物理相關背景，無工作經驗可

1. 電機工程或電子工程相關領域的碩士學位 2. 熟IC/IP電路設計，SRAM經驗尤佳 3. SRAM compiler設計, gds和netlist tiling 4. Characterization of SRAM timing和power 5. 熟linux, spice, laker等軟體

1. NVM電路開發設計。 2. NVM週邊類比電路開發設計與佈局優化。 3. NVM電路整合開發設計。 4. 協助NVM測試晶片偵錯、驗證。 5. 協助客戶嵌入使用以及導入量產NVM IP產品。 研究所以上電子/電機相關系所畢，專長於類比電路設計、固態電子或功率半導體元件設計，有下線經驗者優先考慮。

1.具類比IC設計經驗 2.具ADC、DAC、PLL、High Speed Serial Link 等相關類比IC設計經驗者佳 3.諳低雜訊設計，具晶片整合經驗者佳 4.溝通表達能力佳，喜好腦力激盪，具團隊合作態度者

【工作內容】 1. HLS高階語言電路設計 2. 影像處理演算法研究 3. Verilog/VHDL 電路設計相關經驗 4. FPGA開發與設計 【知識/經驗/技能要求】 1. HLS design experience will be best. 2. C/C++ language development experience 3. Image processing algorithm experience. 4. Xilinx FPGA design experience. 【個人特質】 1. 個性好相處，善於團隊合作、個性嚴謹者佳。

我們專注於能源晶片與深度演算法的融合創新，誠徵類比IC演算法工程師，將傳統的手工類比設計流程轉化為自動化的智慧演算法，讓電路設計更高效、更穩定，推動類比設計的未來。 你將負責： 開發電路拓撲分析演算法 設計 sizing 最佳化演算法（基於 gm/Id methodology 等） 將手工設計流程轉化為程式化流程 協助建立類比IC設計自動化工具 與軟體團隊合作進行演算法驗證與優化 熟練使用 Vibe Coding 工具（Cursor、Github Copilot、Claude… 等）更佳 我們期待你具備： 類比IC設計實務經驗 熟悉運算放大器、ADC/DAC、電源管理電路等拓撲設計 精通 SPICE 模擬與電路參數萃取 深度理解 sizing methodology（如 gm/Id 設計法） 能清楚闡述設計 trade-off 與電路原理 加分條件： 具備 Python 程式能力 有將手工設計方法轉換為程式實現的經驗 具備統計分析能力（Monte Carlo / corner analysis） 有 EDA 工具 API 開發經驗 熟悉圖論演算法與資料結構 如果你熱愛把設計方法變成程式，並用演算法重新定義類比IC設計的可能性，歡迎加入我們！

【成為円星人】 円星科技由一群專業與充滿熱情的夥伴創立於2011年，為積體電路矽智財設計服務業之新秀，秉持著『成為半導體業最值得信賴之IP公司』的願景，追求永續經營與成長。 誠摯歡迎您成為円星人，加入我們，站上國際舞台！ 一起共同打拚，以精品文化之精神，創造價值，追求卓越！ 【職務簡介】 M31主要業務為向 IC 設計業者和晶圓代工廠授權 IP，此職務為負責高速介面 IP（High Speed Interface IP）, 包含USB. PCIE 等SERDES IP設計工程師職缺。 【將負責的工作內容】 1. High-speed interface analog circuit design (TX, RX, etc) 2. Clocking related circuit design：PLL/CDR 3. Integrate mixed signal IP and handle co-simulation 【條件與特質】 1. 有類比IC設計工程師相關工作經歷5年以上 2. 電機電子/資訊工程碩士畢業 如果您有以上相關經驗且對此職缺有興趣，歡迎投遞您的履歷！

【產品範疇】 1.Touch panel controller 2.TDDI 【工作內容】 1.Analog front-end design 2.ADC design 3.Switched-capacitor circuit design 4.負責layout floorplan規劃，與layout工程師合作完成相關驗證 【需求條件】 1.Device physics knowledge applied to analog IC design 2.Familiar with analog IC design flow 3.Familiar with Hspice or Spectre

1. Logic NVM, SONOS 記憶體電路開發設計(Array, Decoding, Sense Amplifier等電路) 2. 記憶體電路整合開發設計。