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「Analog IC technical manager」的相似工作

聚睿電子股份有限公司
共500筆
10/14
新竹縣竹北市3年以上碩士以上
1. 顯示驅動IC 類比電路設計 2. 電源管理IC 類比電路設計 3. 高速介面 類比電路設計 4. 觸控類比前端感測類比電路設計
應徵
10/13
鋒迪亞股份有限公司其他半導體相關業
台中市西屯區1年以上專科
我們專注於能源晶片與深度演算法的融合創新,誠徵類比IC演算法工程師,將傳統的手工類比設計流程轉化為自動化的智慧演算法,讓電路設計更高效、更穩定,推動類比設計的未來。 你將負責: 開發電路拓撲分析演算法 設計 sizing 最佳化演算法(基於 gm/Id methodology 等) 將手工設計流程轉化為程式化流程 協助建立類比IC設計自動化工具 與軟體團隊合作進行演算法驗證與優化 熟練使用 Vibe Coding 工具(Cursor、Github Copilot、Claude… 等)更佳 我們期待你具備: 類比IC設計實務經驗 熟悉運算放大器、ADC/DAC、電源管理電路等拓撲設計 精通 SPICE 模擬與電路參數萃取 深度理解 sizing methodology(如 gm/Id 設計法) 能清楚闡述設計 trade-off 與電路原理 加分條件: 具備 Python 程式能力 有將手工設計方法轉換為程式實現的經驗 具備統計分析能力(Monte Carlo / corner analysis) 有 EDA 工具 API 開發經驗 熟悉圖論演算法與資料結構 如果你熱愛把設計方法變成程式,並用演算法重新定義類比IC設計的可能性,歡迎加入我們!
應徵
10/15
新北市泰山區3年以上碩士
記憶體power system 設計 『具工作經驗者,薪資另議』
應徵
09/20
新竹市3年以上碩士以上
1. Main responsibility is to design analog IPs in MCU such as adc/dac, pll, osc, por, ldo 2. 具備DC-DC Converter, Buck相關電路設計 2. Responsible for analog IP design, verification plan, test plan, document 3. Communicate with system, layout and digital engineer to ensure high quality --------------------------------------------------------------------------------------- 雅特力科技創立於2016年,為智原科技子公司。 【Artery雅特力】即將在台上市的IC設計公司,主要產品為32bit ARM core base MCU 公司網址:https://www.arterychip.com 關於雅特力:https://www.104.com.tw/company/1a2x6blojm
應徵
10/14
新竹縣寶山鄉經歷不拘碩士
1.LPDDR4/DDR4/DDR3 Mixed signal SERDES/PLL相關開發工作 2.Mixed signal SERDES RTL behavior analysis and implement,熟悉HSPICE 並具備 std cell design flow基礎佳
應徵
10/14
新北市汐止區6年以上碩士以上
類比電源IC設計、電路模擬、IC驗證、熟悉佈局規劃及良率提升。 熟悉下列產品的開發及設計: 1.Buck/Boost/Buck-Boost controller/converter 2.LDO/ Power Switch/ OPAMP/ 3.Switching Charger IC 4.High voltage Gate Driver for Motor 5.Low voltage Gate Driver 辦公地點分為 1.新北汐止辦公室(台灣科學園區T3館) 2.新竹竹北辦公室(富翼大樓)
應徵
10/13
新竹市2年以上碩士以上
We are seeking a skilled Analog IC Design Engineer with expertise in MIPI TX/ PLL design and sensor readout circuits. The ideal candidate will possess a strong foundation in analog design and a passion for developing cutting-edge solutions in a collaborative environment. 1.Design and implement MIPI TX and PLL circuits for high-speed data transmission. 2.Develop charge pump and LDO (Low Dropout Regulator) circuits to ensure efficient power management. 3.Design and optimize oscillator (OSC) circuits for precise timing applications. 4.Create sensor readout circuits, including CDS (Correlated Double Sampling), TDC (Time-to-Digital Converter), ramp circuits, DAC (Digital-to-Analog Converter), and comparators. 5.Collaborate with system engineers to define specifications and ensure alignment with overall project requirements. 6.Perform circuit simulations and analyses using tools such as Cadence, Spectre, or HSPICE. 7.Conduct design verification and validation through prototyping and testing. 8.Optimize designs for performance, power efficiency, and reliability. 9.Participate in design reviews and contribute to project documentation. 10.Provide support during the layout and fabrication process. Preferred Qualifications: 1.Familiarity with IP design principles. 2.Experience with mixed-signal circuits. 3.Knowledge of low-noise and high-speed design techniques.
應徵
10/14
新竹縣竹北市3年以上碩士以上
1.顯示類比電路設計與整合(whole chip integration) 2.顯示類比電路設計,如: Bandgap, Charg pump, LDO, Gamma, Source driver, GOA
應徵
10/13
新竹縣竹北市經歷不拘碩士以上
1. SAR ADC / Current steering DAC/ SDM ADC/ DAC related 2. Analog Baseband related 3. 據有類比整合相關經驗佳
應徵
10/13
新竹縣竹北市2年以上碩士以上
1.研究、設計、模擬與驗證類比及NVM IC電路。
應徵
10/13
新竹縣竹北市1年以上碩士以上
Analog IC design (A) Power Management(SMPS, Buck, Boost, LDO, Battery Charger), (B) Analog Circuit Design
應徵
10/09
新北市新店區經歷不拘碩士以上
1. MSEE is required. 2. Solid background in analog integrated circuits. 3. Knowledge of high speed serial link technology. 4. Familiar with SerDes PHY (USB, PCIE Express, SATA and Thunderbolt) and building block (DFE, CTLE, CDR, PLL and FFE transmitter). 5. Experience in design and simulation high speed transceiver is a plus.
應徵
10/13
新竹市經歷不拘碩士以上
Job description Join our innovative team specializing in cutting-edge embedded memory solutions. We are seeking Analog Circuit Engineers to play a key role in the design and development of high-performance embedded DRAM and associated peripheral circuits. In this position, you will be responsible for the complete cycle of DRAM circuit design and simulation verification. Your tasks will involve developing novel circuit topologies, transistor-level design, optimizing performance metrics, and ensuring robust functionality through extensive simulations using industry-standard EDA tools. Required qualifications include a strong technical background in Electrical Engineering, Electronics Engineering, Computer Engineering, Physics, or a closely related field. Candidates must possess demonstrated, significant experience in DRAM circuit design and comprehensive simulation verification methodologies. Ideally, candidates will have proven design experience in specific DRAM-related circuit blocks, including but not limited to: Row and Column Decoder circuits Control path logic DC-DC converters, Charge Pumps, and Bandgap References Delay Locked Loops (DLLs) and Phase Locked Loops (PLLs) Negative voltage generators (NVG) and other critical peripheral circuits This is an excellent opportunity to contribute to state-of-the-art embedded memory designs in a dynamic, collaborative environment. If you are a skilled analog designer passionate about solving complex challenges in DRAM circuitry, we encourage you to apply and help shape the future of embedded memory technology.
應徵
08/27
新竹市1年以上碩士
(1) DRAM電路設計與模擬驗證 (2) 具備DRAM ROW/COLUMN/CONTROL/DC/DLL任一或更多電路設計經驗者佳 (3) 具備verilog經驗者尤佳 (4) 了解基本UNIX操作,具備AWK等Programing能力者尤佳 (5) 具備電機電子資訊物理相關背景,無工作經驗可
應徵
10/16
新竹縣竹北市3年以上碩士以上
【成為円星人】 円星科技由一群專業與充滿熱情的夥伴創立於2011年,為積體電路矽智財設計服務業之新秀,秉持著『成為半導體業最值得信賴之IP公司』的願景,追求永續經營與成長。 誠摯歡迎您成為円星人,加入我們,站上國際舞台! 一起共同打拚,以精品文化之精神,創造價值,追求卓越! 【職務簡介】 M31主要業務為向 IC 設計業者和晶圓代工廠授權 IP,此職務為負責IO電路設計相關之職缺。 【將負責的工作內容】 1. ESD/Latch-up防護設計與驗證 2. I/O電路設計 (Fail safe, Tolerant, Cascade) 3. 高速IO 電路設計 (DDR, ONFI, SDIO) 4. LDO/POR/VDT 電路設計 5. XTAL oscillator 電路設計 6. Analog circuit, IO, PISI, ESD Basic/Advanced Knowledge 【條件與特質】 1. Analog circuit, IO circuit design and simulation 2. 擅長工具-SPICE, Virtuoso 3. 有IO 相關工作經歷3年以上, Analog/IO Basic/Advanced Knowledge 如果您有以上相關經驗且對此職缺有興趣,歡迎投遞您的履歷!
應徵
10/07
新竹縣竹北市3年以上碩士以上
- Responsible for entire analog design implementation that covers design specification, design creation, integration and optimization to layout review, final post-layout simulation, silicon characterization and system test and debug. - Experience in analog IP development that include SERDES, ADC, DAC, Audio Codec, PLL, IO, memory, analog blocks and high speed PHY for 130nm, 90nm and below technologies. - Knowledge in high speed PHY design (PCIE, USB, GbE, DDR, ETHERNET) is an added advantage. - Preferably done some test characterization, measurement and compliance in previous employment
應徵
09/24
新竹縣竹北市5年以上大學以上
Reporting to MOSFET Development Manager, you will work as Sr. MOS Development Engineer to be responsible for process integration, development and optimization. About the job: Work with product designer to create new device structure ideas and develop the necessary Mosfet/ IGBT /Diode technologies Closely work with internal process experts and external foundry partners to set up the required technologies and processes to produce the prototypes and with test labs to assess results vs. simulations / expected behavior. Responsible for experimental matrix design to evaluate and optimize design vs. specification. Co-work with fab engineering teams to generate the final design rule menu and electrical parametric specifications. Participation in fab selection and evaluation for future foundry locations. Participate and help the Design Engineers and Product Engineers on reverse engineering analysis when necessary. Act as the internal expert of semiconductor devices and processes to provide the necessary information and advices to designers on new technologies. Short term travels for business trips and trainings. About you: Knowledge of semiconductor device physics, such as Diode, BJT, MOSFET, and IGBT…etc and understanding of complex interactions between different fabrication processes. Experiences in semiconductor process development, and basic knowledge in semiconductor device characterization. Ability of arranging tests with 3rd party labs and comfortable with working in Lab for device characterization. Good writing/reading/communication in English is a MUST. The ability to operate independently in a cross-cultural working environment. Experiences in both conventional Bipolar, CMOS, DMOS processe Understanding or experiences in power semiconductor devices assembly and applications would be preferred. Knowledge and experiences of material analysis or Failure analysis tools, such as SRP, SIMS, SEM…etc. Familiar with mask generation, wafer fab process flow and in-line/PCM specifications. Knowledge and experience in one or more of the following areas would be a plus, but not must: o Test pattern generation o Semiconductor process/device modeling o Basic assembly & test processes.
應徵
10/10
台北市內湖區經歷不拘碩士以上
Responsible for developing custom IP for SoC design from specification definition, circuit design to testing, and familiar with component and process characteristics.
應徵
10/11
緯創軟體股份有限公司電腦軟體服務業
新竹縣竹北市3年以上專科以上
【職務內容】 ˙需具備HV經驗 Level Shifter(含 HV Device)、Charge Pump、Source Driver、OpAmp / DAC、TCON(含 Digital Layout + Clock Tree) ˙需具備3-5年Driver相關經驗 ˙需熟悉繞線(Routing) ˙Block-Level設計經驗可 ˙能讀懂 Calibre DRC command file 語法佳 ˙具備28/22nm HV製程經驗佳 ˙無需英文能力,全台灣團隊
應徵
10/13
新竹市2年以上碩士以上
Digital IC design engineer - Familiar with Verilog RTL coding - Familiar with digital design flow (pre-layout simulation, timing constraint, synthesis, post-layout simulation) - Will be working on high speed Serdes IPs - Experience or interest in all-digital PLLs or clock-data recovery circuits is a big plus
應徵