1. Main responsibility is to design analog IPs in MCU such as adc/dac, pll, osc, por, ldo
2. 具備DC-DC Converter, Buck相關電路設計
2. Responsible for analog IP design, verification plan, test plan, document
3. Communicate with system, layout and digital engineer to ensure high quality
---------------------------------------------------------------------------------------
雅特力科技創立於2016年,為智原科技子公司。
【Artery雅特力】即將在台上市的IC設計公司,主要產品為32bit ARM core base MCU
公司網址:https://www.arterychip.com
關於雅特力:https://www.104.com.tw/company/1a2x6blojm
類比電源IC設計、電路模擬、IC驗證、熟悉佈局規劃及良率提升。
熟悉下列產品的開發及設計:
1.Buck/Boost/Buck-Boost controller/converter
2.LDO/ Power Switch/ OPAMP/
3.Switching Charger IC
4.High voltage Gate Driver for Motor
5.Low voltage Gate Driver
辦公地點分為
1.新北汐止辦公室(台灣科學園區T3館)
2.新竹竹北辦公室(富翼大樓)
We are seeking a skilled Analog IC Design Engineer with expertise in MIPI TX/ PLL design and sensor readout circuits. The ideal candidate will possess a strong foundation in analog design and a passion for developing cutting-edge solutions in a collaborative environment.
1.Design and implement MIPI TX and PLL circuits for high-speed data transmission.
2.Develop charge pump and LDO (Low Dropout Regulator) circuits to ensure efficient power management.
3.Design and optimize oscillator (OSC) circuits for precise timing applications.
4.Create sensor readout circuits, including CDS (Correlated Double Sampling), TDC (Time-to-Digital Converter), ramp circuits, DAC (Digital-to-Analog Converter), and comparators.
5.Collaborate with system engineers to define specifications and ensure alignment with overall project requirements.
6.Perform circuit simulations and analyses using tools such as Cadence, Spectre, or HSPICE.
7.Conduct design verification and validation through prototyping and testing.
8.Optimize designs for performance, power efficiency, and reliability.
9.Participate in design reviews and contribute to project documentation.
10.Provide support during the layout and fabrication process.
Preferred Qualifications:
1.Familiarity with IP design principles.
2.Experience with mixed-signal circuits.
3.Knowledge of low-noise and high-speed design techniques.
1. MSEE is required.
2. Solid background in analog integrated circuits.
3. Knowledge of high speed serial link technology.
4. Familiar with SerDes PHY (USB, PCIE Express, SATA and Thunderbolt) and building block (DFE, CTLE, CDR, PLL and FFE transmitter).
5. Experience in design and simulation high speed transceiver is a plus.
Job description
Join our innovative team specializing in cutting-edge embedded memory solutions. We are seeking Analog Circuit Engineers to play a key role in the design and development of high-performance embedded DRAM and associated peripheral circuits.
In this position, you will be responsible for the complete cycle of DRAM circuit design and simulation verification. Your tasks will involve developing novel circuit topologies, transistor-level design, optimizing performance metrics, and ensuring robust functionality through extensive simulations using industry-standard EDA tools.
Required qualifications include a strong technical background in Electrical Engineering, Electronics Engineering, Computer Engineering, Physics, or a closely related field. Candidates must possess demonstrated, significant experience in DRAM circuit design and comprehensive simulation verification methodologies.
Ideally, candidates will have proven design experience in specific DRAM-related circuit blocks, including but not limited to:
Row and Column Decoder circuits
Control path logic
DC-DC converters, Charge Pumps, and Bandgap References
Delay Locked Loops (DLLs) and Phase Locked Loops (PLLs)
Negative voltage generators (NVG) and other critical peripheral circuits
This is an excellent opportunity to contribute to state-of-the-art embedded memory designs in a dynamic, collaborative environment. If you are a skilled analog designer passionate about solving complex challenges in DRAM circuitry, we encourage you to apply and help shape the future of embedded memory technology.
- Responsible for entire analog design implementation that covers design
specification, design creation, integration and optimization to layout review, final
post-layout simulation, silicon characterization and system test and debug.
- Experience in analog IP development that include SERDES, ADC, DAC, Audio
Codec, PLL, IO, memory, analog blocks and high speed PHY for 130nm, 90nm and
below technologies.
- Knowledge in high speed PHY design (PCIE, USB, GbE, DDR, ETHERNET) is an
added advantage.
- Preferably done some test characterization, measurement and compliance in
previous employment
Reporting to MOSFET Development Manager, you will work as Sr. MOS Development Engineer to be responsible for process integration, development and optimization.
About the job:
Work with product designer to create new device structure ideas and develop the necessary Mosfet/ IGBT /Diode technologies
Closely work with internal process experts and external foundry partners to set up the required technologies and processes to produce the prototypes and with test labs to assess results vs. simulations / expected behavior.
Responsible for experimental matrix design to evaluate and optimize design vs. specification.
Co-work with fab engineering teams to generate the final design rule menu and electrical parametric specifications.
Participation in fab selection and evaluation for future foundry locations.
Participate and help the Design Engineers and Product Engineers on reverse engineering analysis when necessary.
Act as the internal expert of semiconductor devices and processes to provide the necessary information and advices to designers on new technologies.
Short term travels for business trips and trainings.
About you:
Knowledge of semiconductor device physics, such as Diode, BJT, MOSFET, and IGBT…etc and understanding of complex interactions between different fabrication processes.
Experiences in semiconductor process development, and basic knowledge in semiconductor device characterization.
Ability of arranging tests with 3rd party labs and comfortable with working in Lab for device characterization.
Good writing/reading/communication in English is a MUST.
The ability to operate independently in a cross-cultural working environment.
Experiences in both conventional Bipolar, CMOS, DMOS processe
Understanding or experiences in power semiconductor devices assembly and applications would be preferred.
Knowledge and experiences of material analysis or Failure analysis tools, such as SRP, SIMS, SEM…etc.
Familiar with mask generation, wafer fab process flow and in-line/PCM specifications.
Knowledge and experience in one or more of the following areas would be a plus, but not must:
o Test pattern generation
o Semiconductor process/device modeling
o Basic assembly & test processes.
Responsible for developing custom IP for SoC design from specification definition, circuit design to testing, and familiar with component and process characteristics.
Digital IC design engineer
- Familiar with Verilog RTL coding
- Familiar with digital design flow (pre-layout simulation, timing constraint, synthesis, post-layout simulation)
- Will be working on high speed Serdes IPs
- Experience or interest in all-digital PLLs or clock-data recovery circuits is a big plus