「SoC Design Engineer/ SoC設計工程師」的相似工作

1. 專案規劃與管理 a. 專案前期評估 b. 規劃IC設計各個階段的schedule與人力配置，包括架構設計、RTL設計整合、合成、驗證和測試 c. 確保進度符合計劃，並有效利用團隊的資源來完成項目 d. 與外部供應商及客戶溝通，並與其他部門協作，確保IC設計能夠順利實現並符合最終需求 2. 技術監督與指導 a. 對設計整合流程進行技術監督，確保設計符合公司標準、品質要求，並能夠滿足性能、功耗、面積等要求 b. 確保設計整合的正確性，協調設計驗證過程，包括功能驗證、時序分析、功耗分析等 c. 協助團隊解決在設計整合與驗證時遇到的問題 d.負責 SOC low power 規劃及設計 e.熟悉並負責SOC IP( MIPI、DDR、PCIe 等) 的整合，確保與 SOC 設計的兼容性與效能最佳化 3. 團隊管理與領導 a. 負責指導部門內工程師，分配工作並提供技術指導，協助團隊克服技術挑戰 b. 招募新成員並確保團隊技能持續更新，推動專業發展和培訓計劃 c. 協調團隊內部的工作進度和溝通，確保各個成員的工作能夠高效協作 4. 其它主管交辦事項 【必要條件】 1. 電機、電子、資訊工程或相關科系，碩士以上學歷 2. 10年以上 SoC 設計或整合經驗 3. 熟悉CPU子系統設計整合 a. 熟悉 ARM 架構， b. 對 RISC-V 架構有基本認識 4. 熟悉數位IC前端設計流程，如RTL design、Lint/CDC、Synthesis、STA、LEC、ECO等 5. 熟悉 MIPI、DDR、PCIe、PHY、Serdes、PLL 等常用 IP 的應用與整合 6. 熟悉IC後段設計流程，如DFT、MBIST、P&R、post-cilicon system level debugging等 7. 良好的溝通能力，能與內部 RD 團隊及外包協力廠商有效協作，推動專案如期完成

The successful candidate will work with team members and apply his/her design techniques to work on different phases of complex logic design for ASIC/SOC project. The role will include working on the following tasks from time to time: HDL coding, documentation, RTL quality check, cooperate with back-end engineer etc. 【Key Responsibilities】 - Responsible for front-end digital logic design in ASIC/SOC projects. - Perform HDL coding (Verilog/SystemVerilog). - Prepare and maintain design documentation (specifications and design documents). - Conduct RTL quality checks (Lint, CDC, power analysis, etc.). - Collaborate with Backend/Physical Design engineers to achieve timing closure. 【Core Requirements】 - Education/Experience: Master’s degree with ≥ 2 years, or Bachelor’s degree with ≥ 3 years of digital ASIC/SOC design experience. - RTL Design: Proficient in RTL coding using Verilog/SystemVerilog or VHDL. - TO / Front-End Flow: Familiar with front-end design flow, including synthesis, Lint, CDC, and STA. - EDA Tools: Experience with tools such as Lint, CDC check, and PrimeTime PX (power analysis). - Documentation: Ability to write design specifications and technical documents. - Collaboration: Work closely with the Design Verification (DV) team on IP verification. 【Preferred Qualifications】 - Familiarity with CPU architectures (x86/ARM/8051). - Knowledge of AMBA bus protocols (AXI/AHB/APB). - Understanding of PCIe protocol.digital IP/SOC design verification.

## 職務說明 - 應用於無人機雷達系統 - 數位IP架構設計與實作。 - 透過MATLAB/C++協助數位IP驗證 - 透過FPGA整合與驗證。 ## 技能要求 - 具備數位訊號處理經驗 - 具備數位電路設計經驗 - 程式語言必要：Verilog/VHDL, TCL, ##加分條件： - 具備雷達/通訊訊號處理、數位設計架構 - 具備RF/Analog 知識與RF/Analog校準設計 - 程式語言: MATLAB, python, c, c++, Chisel3

1. Algorithm/Spec to RTL design, verification and synthesis 2. IP FPGA verification 3. Stardand IP configuration, integration and verification 4. Whole chip/Subsystem IP Integration and verification

想找一個能真正發揮實力、與頂尖團隊共同打造未來技術的平台嗎？ 在芯鼎，我們結合 AI 與影像處理技術，開發具突破性的SoC解決方案，應用於自動駕駛、無人機、機器人、AI 與高效能運算等前沿領域。我們以 ARM 架構（基於 ARM Compute Sub-System & SystemReady）為基礎，打造引領未來的先進視覺以及 AI SoC 設計平台。 在這裡，你將有機會： 與資深工程師與跨域團隊合作，挑戰技術極限 深入 AI 系統與 SoC 架構設計，推動產業升級與創新 從 SoC 微架構、設計實作到驗證流程，全面提升技術視野與實戰能力 無論你擅長或有興趣領域 ，是 IC 設計（DE）、驗證開發（DV），先進製程晶片實體設計含前後端優化以及可測試性設計（Physical design ，DFT）。 我們誠摯邀請你加入芯鼎，與我們一起打造改變世界的設計架構平台！ ***最終職稱與職級將依學經歷與專長核定*** 【SoC 平台、IP 整合】職責與技能(3年以上專業經驗) 1. 規劃與實作 SoC 系統架構，執行模組功能驗證與整體平台驗證 2. 整合並驗證各類高速介面與標準 IP，包括：ARM 架構、UCIe、PCIe、DDR、Ethernet、USB、MIPI TX/RX、eDP、Security Engine 等 加分技能： 1. 熟悉晶片開發全流程，涵蓋前端 RTL 設計、驗證，到後端實作與收斂 2. 具備跨模組與跨部門協同整合經驗，能有效推動系統級平台建構與整合效率 【Design Verification (DV)】職責與技能(3年以上專業經驗) 1. 建立並維護模組與系統層級的驗證環境 2. 使用 SystemVerilog 撰寫測試平台，進行功能驗證與模擬分析 3. 撰寫並整合 SystemVerilog Assertions（SVA）以提升驗證覆蓋率與錯誤檢出能力 必要技能： 1. 精通 UVM（Universal Verification Methodology）驗證方法學 2. 熟悉 AMBA 協定（AXI、AHB、APB 等）之功能與驗證應用 3. 熟悉硬體驗證平台，如 Synopsys HAPS, Synopsys ZeBu，具備實際部署或加速驗證經驗者尤佳 【PD/Design for Testability (DFT)】職責與技能(3年以上專業經驗) 1. 實作區塊與整合等級的可測試性設計（包含 DC/AC Scan、Boundary Scan (BSD)、MBIST 與 Repair） 2. 撰寫與維護 DFT 模式下的 SDC，協助 APR 與前端設計團隊完成時序收斂 3. 執行 RTL 等級的綜合（synthesis），並配合 DFT 架構需求整合設計流程 必要技能： 1. 熟悉 Synopsys 或 Mentor 的 DFT 工具與完整設計流程 2. 熟悉 UPF (Unified Power Format) 與 Synopsys 綜合工具（如 Design Compiler） 3. 具備 Scan Stitch、MBIST 修補、自動測試向量生成等相關經驗者優先

Responsibilities: • Develop integrated verification environment. • Verify designs with system verilog and system verilog assertion. • Build, maintain and upgrade testbenches and their components using UVM-based methods. • Check functional coverage and code coverage • Create controlled random testcases. Pre-debug and provide debug reports. • Scripting experience using scripting languages like Perl and Python.

ASIC design engineer responsible for post-RTL design flow. He/She will be responsible for block and /or chip level synthesis, timing closure, DFT generation, and ECOs. The responsibilities include but are not limited to. •    Improve the design methodology and flow. •    Synthesis, timing closure, and DFT support for various types of SerDes IPs ranging from 10Gbps to 224Gbps data rates for different applications. •    Collaborate with Analog/Digital design teams to deliver competitive SerDes IP solutions for all the Marvell product lines. •    Provide support to the product teams, for both pre and post-silicon

1.具FPGA平台開發相關經驗 2.熟Verilog 3.熟顯示器TCON/Driver驅動原理者佳 4.能獨立建立FPGA開發環境平台 5.有數位邏輯IC開發經驗者佳

[job description] Wolley is seeking candidates for a digital design engineer position. You will join an experienced team designing next-generation memory, storage controllers, and high-speed interface standard. You will also contribute to design concept discussion, architecture definition, as well as design implementation. ‧ Architecture design and RTL implementation ‧ System bus and related peripheral designs ‧ SoC and emulation platform design ‧ SoC system performance analysis [Requirement] 1. Bachelor's or Master's degree in Electrical Engineering or related fields 2. Familiar with RTL design, SystemVerilog, front-end design flow 3. The following working knowledge is desired: * Python programming * TCL scripting * Universal Verification Methodology (UVM) * Low power design and analysis

1.數位IP相關功能的設計與實現 2.數位IP仿真與FPGA驗證 3.數位IP/subsys/chip_top的前段整合流程signoff 4.ISO 26262 FMEDA 設計和品質改進 5.與第三方數位 IP 供應商合作

1. 32-bits RISC-V 平台 Driver與Firmware程式開發 2. FPGA與IC驗證 3. 自動化驗證流程開發 4. 主管交付任務

1. 具 0~2年數位晶片設計，或有 0~5年類比晶片設計工作經驗。 2. 具備基本數位和類比電路知識，熟習標準晶片設計流程。 3. 熟習業界常用EDA tools, 或Matlab/ Simulink。 4. 研習過CMOS or BiCMOS 類比設計電路課程，對放大器有基礎認識。 5. Experience in these areas is preferred： * BiCMOS or CMOS high-speed (>20Gb/s) circuit, Linear electrical amplifier & equalizer, High-speed (>25G) CDR/PLL/SerDes. * Linear optical laser driver & receiver (TIA + linear amplifier) 本職位負責類比IC電路的設計、驗證和除錯。這是一個高度技術性的職位，對公司的產品開發至關重要。我們正在尋找一位熱愛類比IC設計並具有相關經驗的人才，以推動公司的技術創新和發展。 如果您對這個職位感興趣，請投遞您的履歷表，我們立即與您聯繫。

(1) DRAM電路設計與模擬驗證 (2) 具備DRAM ROW/COLUMN/CONTROL/DC/DLL任一或更多電路設計經驗者佳 (3) 具備verilog經驗者尤佳 (4) 了解基本UNIX操作，具備AWK等Programing能力者尤佳 (5) 具備電機電子資訊物理相關背景，無工作經驗可

1. Design verification with SystemVerilog/UVM, C/C++ 2. Integration test environment with VIP 3. Develop checker and scoreboard. 4. Verify design with SystemVerilog assertion. 5. Test plan for a verification task. [Requirement] 1. Familiar with SystemVerilog HDL, OOP, Python, TCL, and shell programming. 2. Better to have SoC design and bus concept.

About us: VICI Holdings' Hardware team is seeking a skilled FPGA Engineer to join our dynamic group. In this role, you will be pivotal in advancing our trading systems, contributing to the development and enhancement of cutting-edge technologies. We boast the leading software development team in Taiwan and possess FPGA design technology in parallel with wall street trading firms. This expertise enables us to build low-latency, fully automated trading systems. Our trading strategies cover stocks, futures, and derivatives, achieving a daily global trading volume in the hundreds of millions dollars. Roles/ Responsibilities: • High speed IP interface design (such as PCIE gen 3, 4 / Ethernet, DDR etc.) • In charge of FPGA design/ implementation/simulation. • Transmission protocol layer development. • Optimizing hardware for latency. • Proficiency with Xilinx design environment. Candidate Requirements: • BS/MS degree above from EE, CE with 2+ years of relevant work experience • Experience in high-speed interface design or knowledge in PCIE/ Ethernet/MIPI/DDR design or implementation is a plus • Experience using System Verilog and at least two prior RTL design is a required. • Demonstrated ability to tackle complex design challenges and implement effective solutions Other Requirements: • High self-motivated individual with good communication skill. • English level – working level proficiency is a plus. Interview Process: • Resume selection ->Coding Test -> AI Interview (Online) -> F2F Interview -> HR Manager

1. SOC/IP 整合工作，從RTL到 Netlist 2. clock tree structure design 3. Lint / CDC check / Synthesis/ DFT/ LEC

我們專注於3D影像立體雙目視覺技術 產品應用於3D 影像辨識、360 度環景拍照、攝影或AR 與VR 職務內容： ★ USB2.0/3.1或 MIPI 介面之2D/ 3D 影像處理與壓縮之 IC 開發 ★ 影像處理與壓縮相關數位 IP暨產品之開發設計、測試、驗證 條件要求： 1. 對IP Verification, System Verification 有興趣 2. 熟Verilog coding 與 ASIC design Flow 與 Timing Closure 3. 或有 SoC IC 開發經驗 4. 對開發人工智慧((AI) 晶片與邊緣運算有興趣者

1.根據通訊演算法，撰寫RTL code (Verilog, VHDL) 2.數位電路設計。 3.承辦及參與委託給業界或學界之研發案。

※ Job Contents: 1. DDR/HBM controller IP design 2. DDR/HBM IP customer support 3. Execute digital IP front-end flow ※ Requirements: 1. 3-years digital IC design experiences 2. Senior/Technical Manager: 8-years digital IC design experiences 3. Familiar with DDR protocol is a plus 4. Familiar with AMBA interface is a plus 5. Familiar with IC front-end design flow such as Lint/CDC, Synthesis, LEC/formality, PrimeTime STA is a plus

Position Description: 1. To provide key technical support in digital IC design implementation, product demonstration, and sales presentations. 2. To demonstrate strong ability and to be hands-on in RTL-to-GDSII design methodology, including both challenging low power and high-performance designs. 3. Have real design experience including floorplan and partition, place, CTS, route, STA timing closure, Physical verification, RC extraction, Power Network analysis. 4. Assist in technical evaluation, assessment and delivery of concurrent ASIC/SoC designs. 5. To play a leading role among other team members, while receive little instruction on routine and general assignments. Position Requirements: 1. A bachelor's degree is essential and 3+ years’ experience in IC design, electronic engineering or computer science applications. 2. Ability to understand and articulate technical issues, (and knowledge of) design products and their applications. 3. Requires working knowledge of one or more programming languages, and effective communication and soft skills. 4. An MS degree and/or working experience in multi-nation IC design house/or familiar with EDI/Innovus product is a plus. 5. Good communication in English and good work attitude. 6. Be familiar with shell/Perl/Tcl etc. script language.