「Sr. APR Engineer(竹北)」的相似工作

【主要工作內容】 1.Netlist to GDS, including floorplan/powerplan/physical synthesis/clock tree synthesis & routing 2.Chip level physical verification, including DRC/LVS/DFM & tapeout 3.IR-Drop analysis 【需求條件】 1.有使用過ICC/ICC2/laker, 曾做過fully layout & chip level PV 2.工作態度積極認真, 有獨自解決問題能力

【本職缺優先審核至高通官網投遞人選】請至高通官網上傳英文履歷表https://careers.qualcomm.com/careers/job/446705989572 【Talents who apply job through Qualcomm Career Website will be reviewed and considered as top priority】 https://careers.qualcomm.com/careers/job/446705989572 【General Summary】 As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm CPU Engineer, you will lead innovative Central Processing Unit (CPU) design efforts that have a critical impact on industries across the world. Qualcomm Engineers collaborate with cross-functional teams to design, verify, and implement multi-core CPU operations for all Qualcomm Business Units. 【Roles and Responsibilities】 • Collaborate with cross-functional teams (RTL, Physical Design, Circuits, CAD) to address critical physical design challenges in CPU implementations. • Develop innovative techniques within Physical Design and optimization space to meet stringent PPA targets. • Coordinate with CPU Software, Architecture, and RTL teams to understand various CPU use cases and propose impactful PPA optimizations. • Engage with external CAD tool vendors and internal CAD teams to identify and enhance optimization issues related to CPU designs. • Partner with all block-level implementation teams to analyze, implement, and improve optimization methods relevant to the designs. • Partner with Process, SoC and Post-silicon teams to analyze, improve design implementations. 【Must have skill/experience】 • Experience with Synthesis, place and route and signoff timing/power analysis. • Knowledge of high performance and low power implementation techniques • Proficiency in scripting (TCL, Python, Perl) 【Minimum Qualifications】 • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 6+ years of Hardware Engineering, Electrical Engineering, or related work experience. OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 4+ years of Hardware Engineering, Electrical Engineering, or related work experience. OR PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field and 3+ years of Hardware Engineering, Electrical Engineering, or related work experience.

RTL design/Verilog behavior model development APR flow support CAD/CAE internal flow/script maintenance

DESCRIPTION: 1. Responsible for the physical design process of chip numbers from netlist to GDSII 2. Responsible for interaction with the front-end design team to realize the design convergence and optimization of the front and back ends; Comprehensive, static timing analysis 3. Floor planning, power planning and signoff, place and route, timing closure, chip static timing analysis and physical verification 4. IP integration, synthesis, verification and correction 5. Other Assigned Tasks delivered by the Line Manager QUALIFICATIONS: 1. MS degree in EE or related. 2. Familiar with physical design flow, including hierarchical design and low power design is a plus 3. Familiar with EDA tools, such as SoC Encounter/INNOVUS/ICC/ICC2 is a plus 4. Familiar with computer languages such as Perl/TCL/C-shell 5. Self-motivated with good communication skills and team spirit 6. Ability to understand and articulate technical issues. 7. Fluent English is a plus. 8. Experience in 12/5nm design is a plus.

1. FrontEnd flow development. 2. Project support and consultant. 3. Develop CAD utility, design automation 4. Work with different process nodes, develop the design flow and methodology

1.Support Design Engineer on Signal Integrity testing and Debugging on Chip and Demo Board 2.Support Customer projects design-in stage to mass-production. 3.Support Customer projects design review (Schematics, layout, CTS report) 4.Team work with RD, AE and QA on debugging and problems solve.

-Working with IC design team on IC bring up and electrical verifications. -Develop evaluation hardware platforms, reference schematic and PCB board verification. -BOM cost and competition analysis. -Technical support for customer projects along with AE/DE/SW/FW/QC engineers.

1. 辦理股務相關作業及股務代理機構溝通窗口 2. 公開資訊觀測站重大訊息(中英文版)及各項公告申報 3. 協助安排董事會、功能性委員會、股東會及相關作業 4. 協助公司治理評鑑及相關作業執行 5. 永續資訊揭露、維護及優化: 彙編年報及股東會議事資料、永續報告書編製及查證作業 6. 其他主管交辦工作事項 1. Handle Employee stock option plan and stock affairs-related operations. 2. File material information and various announcements on the Market Observation Post System (MOPS). 3. Arrange and assist with shareholders’ meetings and other related meetings and tasks. 4. Assist in the implementation of corporate governance evaluations. 5. Disclose, maintain, and enhance sustainability information. 6. Support departmental operations and handle assignments from supervisors.

1. 需具備類比IC Layout、BCD Prcoess整合經驗。 2. 需負責全晶片整合佈局和驗證 3. 熟悉Virtuoso, Laker, Calibre使用 4. 此職務上班地點在新竹辦公室

1. 熟練Autocad 電腦繪圖操作 2. 具備介面協調討論能力。 3. 其他主管交辦行政事項。

1.Analog & physical design flow/script development 2.IR/EM sign-off 3.Flip-chip design 4.Physical verification flow

1. Support customer projects from design-in, design-through to mass-production. 2. Team work with AE, FAE, RD and QA to solve problems.

1. Knowledge and experience of circuit design guideline, latch up, EM and ESD checking rule. 2. Calibre DRC/LVS/PERC Command File maintain and writing. 3. Physical Verification flow enhancement and deployment. 4. CAD Utility development. 5. Soft skill ability like TCL, Perl, shell script

• Co-work with package design team to complete a substrate layout that will meet the design objectives for performance, cost and quality. • Co-work with SOC team to complete Bump floorplan and RDL routing. • Power mesh/power density flow development and related flow development and enhancement. • Provide power plan result for PR team. • Chip IR signoff : provide the result and solution to APR & package team • Chip level PEM/SEM simulation and fixing plan providing. • SIR/DIR/PEM/SEM result data review and verification. • Familiar with Voltus / Redhawk experience is required.

1. 規劃公司產品ESD可靠度驗證計畫 2. 應對客戶及公司內ESD可靠度相關問題 3. 可靠度計算,ESD 產品可靠度風險評估

1) FPGA synthesis, verification, and env. maintain一年以上FPGA使用經驗 2) CP/PT pattern creation and chip validation 3) 熟CMOS原理&CCM設計 4) 懂基礎C/C++,基礎Linux. 5) 編寫技術文件 ,電路設計,IC 訊號測試&功能量測

1. 專案規劃與管理 a. 專案前期評估 b. 規劃IC設計各個階段的schedule與人力配置，包括架構設計、RTL設計整合、合成、驗證和測試 c. 確保進度符合計劃，並有效利用團隊的資源來完成項目 d. 與外部供應商及客戶溝通，並與其他部門協作，確保IC設計能夠順利實現並符合最終需求 2. 技術監督與指導 a. 對設計整合流程進行技術監督，確保設計符合公司標準、品質要求，並能夠滿足性能、功耗、面積等要求 b. 確保設計整合的正確性，協調設計驗證過程，包括功能驗證、時序分析、功耗分析等 c. 協助團隊解決在設計整合與驗證時遇到的問題 d.負責 SOC low power 規劃及設計 e.熟悉並負責SOC IP( MIPI、DDR、PCIe 等) 的整合，確保與 SOC 設計的兼容性與效能最佳化 3. 團隊管理與領導 a. 負責指導部門內工程師，分配工作並提供技術指導，協助團隊克服技術挑戰 b. 招募新成員並確保團隊技能持續更新，推動專業發展和培訓計劃 c. 協調團隊內部的工作進度和溝通，確保各個成員的工作能夠高效協作 4. 其它主管交辦事項 【必要條件】 1. 電機、電子、資訊工程或相關科系，碩士以上學歷 2. 10年以上 SoC 設計或整合經驗 3. 熟悉CPU子系統設計整合 a. 熟悉 ARM 架構， b. 對 RISC-V 架構有基本認識 4. 熟悉數位IC前端設計流程，如RTL design、Lint/CDC、Synthesis、STA、LEC、ECO等 5. 熟悉 MIPI、DDR、PCIe、PHY、Serdes、PLL 等常用 IP 的應用與整合 6. 熟悉IC後段設計流程，如DFT、MBIST、P&R、post-cilicon system level debugging等 7. 良好的溝通能力，能與內部 RD 團隊及外包協力廠商有效協作，推動專案如期完成

Position Description: 1. To provide key technical support in digital IC design implementation, product demonstration, and sales presentations. 2. To demonstrate strong ability and to be hands-on in RTL-to-GDSII design methodology, including both challenging low power and high-performance designs. 3. Have real design experience including floorplan and partition, place, CTS, route, STA timing closure, Physical verification, RC extraction, Power Network analysis. 4. Assist in technical evaluation, assessment and delivery of concurrent ASIC/SoC designs. 5. To play a leading role among other team members, while receive little instruction on routine and general assignments. Position Requirements: 1. A bachelor's degree is essential and 3+ years’ experience in IC design, electronic engineering or computer science applications. 2. Ability to understand and articulate technical issues, (and knowledge of) design products and their applications. 3. Requires working knowledge of one or more programming languages, and effective communication and soft skills. 4. An MS degree and/or working experience in multi-nation IC design house/or familiar with EDI/Innovus product is a plus. 5. Good communication in English and good work attitude. 6. Be familiar with shell/Perl/Tcl etc. script language.

Overview: The Senior TCAD Engineer will be a key member of our technology development team, responsible for advanced modeling and simulation of semiconductor devices and fabrication processes. This role involves defining and executing TCAD projects for novel device architectures, optimizing performance, and analyzing results to guide process integration and design teams. Key Responsibilities: • Develop and validate TCAD models for advanced technology nodes. • Run simulations to assess device performance (IV, CV, breakdown, reliability). • Interpret results to guide design and process improvements. • Collaborate with engineering teams to align on technology roadmap. • Act as TCAD expert and provide technical support. • Automate simulation tasks using scripting (Python, Perl, TCL). • Compare simulations with silicon data and resolve discrepancies. • Prepare technical reports and present to cross-functional teams. • Stay updated on TCAD trends and enhance modeling capabilities. • Mentor junior engineers and contribute to IP development. Qualifications: • 5+ years of hands-on experience in TCAD process and device simulation within the semiconductor industry. • Deep understanding of semiconductor device physics and fabrication processes. • Expertise with commercial TCAD simulation tools such as Synopsys Sentaurus or Silvaco Atlas. • Proficiency in scripting languages (e.g., Python, Perl, TCL) for tool automation. • Experience with analog focused process technologies, particularly high voltage transistors such as drain extended CMOS or LDMOS devices.

【產品線描述】 高速傳輸 (USB4.0、DisplayPort、PCIe、HDMI) IC 【工作說明】 1. Analyze competitor and marketing trend. 2. Determine large scale, define project scope and objectives. 3. Engage of key customer’s project and business development. 4. Estimate the OEM’s RFQ to find the adequate applications & products. 5. New IC feasibility evaluation. 6. Develop/manage a detailed project progress and work plan in order to monitor the schedule on time/track/milestone achievement/areas for improvement. 7. Handle technical communications (FW design/USB roadmap/platform engagement) between RD & clients. 8. Coordinate the cross functional team for solutions of problems/issues when the product design in for qualification. 【必要條件】 1. Product and technical marketing relevant work experience. 2. Familiar with IC design flow and IC cost evaluation. 3. Excellent presentation and PPT design/preparation skill. 4. Outgoing and proactive personality. 5. Excellent verbal and written communication ability in both Mandarin and English.