「Sr. APR Engineer(竹北)」的相似工作

1. Be responsible for setting up and tuning the Linux system corresponding to EDA platform. 2. Be responsible for the daily maintenance of the servers, network equipment and related application components to ensure the reliable operation of the system. 3. Troubleshoot hardware and software errors by running diagnostics, documenting problems and resolutions, prioritizing problems, and assessing impact of issues. 4. Be responsible for collecting data from servers and systems and able to provide various reports based on this data to display operational status.

【主要工作內容】 1.Netlist to GDS, including floorplan/powerplan/physical synthesis/clock tree synthesis & routing 2.Chip level physical verification, including DRC/LVS/DFM & tapeout 3.IR-Drop analysis 【需求條件】 1.有使用過ICC/ICC2/laker, 曾做過fully layout & chip level PV 2.工作態度積極認真, 有獨自解決問題能力

RTL design/Verilog behavior model development APR flow support CAD/CAE internal flow/script maintenance

1. 參與公司數位後段設計 之產品開發 2. 熟悉與維護 並參與 新流程之開發

• Set up x86 and SoC platforms for electrical and functional validation. • Set up thermal solutions, debugger, oscilloscopes, and power measurement equipment. • Execute test plan on engineering systems that involve stress testing, functional testing, power measurements, etc. • Independently manage a group of systems to ensure stability and uninterrupted operation. • Assist in debug of basic PCB, chip, and network issues; document observations and report result to help resolve issues. Basic scripting that includes modifying existing automation scripts where applicable Collect data/execute test plan for chip screening and fusing Collect data from large number of systems, verify logs, identify failures/marginalities/outliers and report to the function owner. • Measure power and collect logs using DAQ/DMM • Maintain inventory and shipping logistic

1. FrontEnd flow development. 2. Project support and consultant. 3. Develop CAD utility, design automation 4. Work with different process nodes, develop the design flow and methodology

Be a chip architecture planner to provide a competitive and valuable solution to sales and customers. This role will consolidate a project scope by achieving technology feasibility and competitiveness study, resource and schedule planning, cost break down for quotation. Responsibility: 1. Pre-sale technical tasks and RFQ follow up. 2. Architecture planner to propose total solution of algorithm, design, IP, P&R, software, process, package, testing, yield and reliability with respect to application scenarios and RFQ. 3. Assessment to the feasibility, competitiveness and risk of proposed total solution. 4. Share solution knowledge base of historical projects within focused fields. 5. Connect and coordinate cross-departments with customers for solution proposal. 6. Project schedule planning and resource evaluation. 7. Cost break down for quotation proposal.

【產品範疇】 Mobile/TCON - LCD display driver、OLED display driver Tablet - LCD display driver TV/NB -LCD display driver TCON 產品 【工作內容】 1.DRC/LVS Command file 撰寫&Maintain 2.Laker TF/UDD/PCELL 撰寫 3.PERC rule & 程式的開發 4.Analog design flow development 5.Shell/SKILL/TCL/Python 程式開發 6.新製程廠內的PDK development 7.In house Utility 開發 8.AI 輔助工具的開發與評估

工作項目： 1. CPU & GPU Backend Implementation (APR) 2. CPU/GPU Backend Flow Development, Enhancement & Automation 3. Advanced CPU/GPU Technology Development: High-performance, Low Power, and PPA Optimization 應徵條件： 1. 碩士以上；電機、資工、電子相關科系畢業為主。 2. 熟悉 APR Tools (Innovus、ICC2、Fusion Compiler…)，有Synthesis、STA/IR Analysis、Physical Verification等相關經驗者佳。 3. 具備程式設計能力，熟悉 TCL/Perl/C++/Python。 4. 有 High Performance CPU/GPU APR經驗尤佳。 5. 個性積極負責、勇於迎接新挑戰，對於 High-Performance CPU/GPU Technology 有興趣者。

1. 專案規劃與管理 a. 專案前期評估 b. 規劃IC設計各個階段的schedule與人力配置，包括架構設計、RTL設計整合、合成、驗證和測試 c. 確保進度符合計劃，並有效利用團隊的資源來完成項目 d. 與外部供應商及客戶溝通，並與其他部門協作，確保IC設計能夠順利實現並符合最終需求 2. 技術監督與指導 a. 對設計整合流程進行技術監督，確保設計符合公司標準、品質要求，並能夠滿足性能、功耗、面積等要求 b. 確保設計整合的正確性，協調設計驗證過程，包括功能驗證、時序分析、功耗分析等 c. 協助團隊解決在設計整合與驗證時遇到的問題 d.負責 SOC low power 規劃及設計 e.熟悉並負責SOC IP( MIPI、DDR、PCIe 等) 的整合，確保與 SOC 設計的兼容性與效能最佳化 3. 團隊管理與領導 a. 負責指導部門內工程師，分配工作並提供技術指導，協助團隊克服技術挑戰 b. 招募新成員並確保團隊技能持續更新，推動專業發展和培訓計劃 c. 協調團隊內部的工作進度和溝通，確保各個成員的工作能夠高效協作 4. 其它主管交辦事項 【必要條件】 1. 電機、電子、資訊工程或相關科系，碩士以上學歷 2. 10年以上 SoC 設計或整合經驗 3. 熟悉CPU子系統設計整合 a. 熟悉 ARM 架構， b. 對 RISC-V 架構有基本認識 4. 熟悉數位IC前端設計流程，如RTL design、Lint/CDC、Synthesis、STA、LEC、ECO等 5. 熟悉 MIPI、DDR、PCIe、PHY、Serdes、PLL 等常用 IP 的應用與整合 6. 熟悉IC後段設計流程，如DFT、MBIST、P&R、post-cilicon system level debugging等 7. 良好的溝通能力，能與內部 RD 團隊及外包協力廠商有效協作，推動專案如期完成

【成為円星人】 円星科技由一群專業與充滿熱情的夥伴創立於2011年，為積體電路矽智財設計服務業之新秀，秉持著『成為半導體業最值得信賴之IP公司』的願景，追求永續經營與成長。 誠摯歡迎您成為円星人，加入我們，站上國際舞台！ 一起共同打拚，以精品文化之精神，創造價值，追求卓越！ 【職務簡介】 M31主要業務為向 IC 設計業者和晶圓代工廠授權 IP，此職務為負責High Speed interface相關PHY IP進行電氣特性驗證(測試), 功能驗證(測試)之職缺。 【將負責的工作內容】 1. USB, SATA , PCI-e , MIPI PHY 高速I/O介面之電氣特性量測 2. PCB board design for High-Speed I/O interface 3. FPGA board design for High-Speed I/O platform 4. USB, SATA, PCI-e, MIPI C/D/M-PHY高速I/O介面之認證測試 5. 協助Analog/Digital RD進行testchip測試 6. 與合作廠商之Controller進行系統整合驗證與測試 7. 協助客戶進行 FPGA驗證 與 客戶產品之初期驗證 【條件與特質】 1. 擅長工具： -EMC/EMI -FPGA -OrCAD -PowerPCB -USB技術 2. 熟悉USB, SATA, PCI-e, MIPI等高速I/O介面之電氣特性與認證流程 3. 熟悉高速示波器,BERT, ENA & AWG 4. 測試自動化程式(Labview)之規劃與撰寫(option) 5. 認真負責、配合度高 6. Any of following experience are plus -PCB Layout -PCB焊接 7. 有 TV Engineer 相關工作經歷 5 年以上 8. 電機電子相關科系碩士畢業 如果您有以上相關經驗且對此職缺有興趣，歡迎投遞您的履歷！

• Co-work with package design team to complete a substrate layout that will meet the design objectives for performance, cost and quality. • Co-work with SOC team to complete Bump floorplan and RDL routing. • Power mesh/power density flow development and related flow development and enhancement. • Provide power plan result for PR team. • Chip IR signoff : provide the result and solution to APR & package team • Chip level PEM/SEM simulation and fixing plan providing. • SIR/DIR/PEM/SEM result data review and verification. • Familiar with Voltus / Redhawk experience is required.

1. 需具備類比IC Layout、BCD Prcoess整合經驗。 2. 需負責全晶片整合佈局和驗證 3. 熟悉Virtuoso, Laker, Calibre使用 4. 此職務上班地點在新竹辦公室

Position Responsibilities Deliver the certification of the Cadence Innovus Platform on cutting-edge foundry process technologies, ensuring optimal performance and reliability. Collaborate closely with Cadence RD and foundry partners to deliver robust, high quality digital design solutions that meet the evolving needs of mutual customers Analysis, communication, and resolution of complex technical challenges encountered by foundry customers, ensuring timely and effective support. Position Qualifications Computer science or EE related Being familiar with Cadence Innovus digital implementation technologies is much preferred Effective interpersonal communication and analytical skills are essential Good communication of oral and written English is required Passion, patience, teamwork, and customer focus. “Can-Do” attitude

【產品線描述】 高速傳輸 (USB4.0、DisplayPort、PCIe、HDMI) IC 【工作說明】 1. Analyze competitor and marketing trend. 2. Determine large scale, define project scope and objectives. 3. Engage of key customer’s project and business development. 4. Estimate the OEM’s RFQ to find the adequate applications & products. 5. New IC feasibility evaluation. 6. Develop/manage a detailed project progress and work plan in order to monitor the schedule on time/track/milestone achievement/areas for improvement. 7. Handle technical communications (FW design/USB roadmap/platform engagement) between RD & clients. 8. Coordinate the cross functional team for solutions of problems/issues when the product design in for qualification. 【必要條件】 1. Product and technical marketing relevant work experience. 2. Familiar with IC design flow and IC cost evaluation. 3. Excellent presentation and PPT design/preparation skill. 4. Outgoing and proactive personality. 5. Excellent verbal and written communication ability in both Mandarin and English.

Position Description Develop PEGASUS/PVS DRC, FILL, LVS, LPE rule decks and RCX flow for worldwide foundries. Manage onsite technical qualification to ensure both PEGASUS/PVS decks and tools are officially qualified by foundries. Collaborate closely with early adoption customers to track and resolve product issues Establish communication channels with R&D to capture customer needs and requirement spec. Work with R&D to enhance and improve PEGASUS/PVS, positioning it as a leading edge Physical Verification tool Position Requirements B.S. in Electrical Engineering (EE), Computer Science (CS), or related area (or equivalent) and 3 - 5 years of experience with Physical Verification tool support/development OR M.S. in EE or CS, or related area (or equivalent) and 1 - 3 years of experience with Physical Verification tool support/development Profound knowledge with Foundry Design Rules and semiconductor fabrication process Ability to develop PEGASUS/PVS rule deck for worldwide foundries, ensuring quality, performance, and compliance with schedules and qualification requirements. Proficiency in TCL and PERL scripting is required Strong English communication skills. Software development experience preferred; familiarity with Cadence SKILL programming is a plus. Experience with IC design and CAD support is advantageous.

Your Job Molex is seeking a Senior PCB Layout Engineer to join our Optical Solutions Business Unit (OSBU). In this role, the successful candidate will be part of a world-class engineering team, contributing to the design and development of next-generation coherent and PAM4 optical transceivers. The Senior PCB Layout Engineer will be responsible for creating high-speed, high-density PCB layouts that meet stringent signal integrity, power integrity, and thermal requirements. This role involves close collaboration with electrical, mechanical, optics and process integration engineers across global teams to ensure optimal performance, manufacturability, and reliability of our advanced optical transceiver modules. Our Team R&D Optoelectronic Solutions What You Will Do - Lead multi-layer PCB layout design for high-speed optical transceivers (e.g., QSFP-DD, OSFP). - Translate complex schematics into production-ready layouts using EDA tools. - Define layout constraints, stack-ups, and component placement in collaboration with cross-functional teams. - Support board bring-up and debug through layout reviews, lab measurements, and issue resolution. - Ensure compliance with DFM, DFT, and IPC standards; coordinate with vendors to address fab and assembly issues. - Generate and manage all fabrication and assembly outputs (Gerbers, ODB++, BOMs, drawings). - Mentor junior engineers and drive continuous improvement in layout processes and design practices. Who You Are (Basic Qualifications) - Bachelor's degree in Electrical Engineering, Electronics Engineering, or a related field. - More than 8 years of hands-on PCB layout experience in high-speed digital or optical communication products. - Proficient in Allegro PCB design software. - Strong knowledge of high-speed signal integrity, power integrity, PCB stack-up design, and layout best practices. - Experience with interfaces such as SerDes (e.g., 112G/224G PAM4), I²C, SPI, MDIO, and power delivery networks. - Familiarity with EMI/EMC mitigation techniques and thermal design considerations. - Solid understanding of PCB fabrication and assembly processes. What Will Put You Ahead - Experience with 800G & 1.6T optical transceiver PCB layout. - Familiarity with signal and power integrity simulation tools (e.g., Sigrity, Ansys, HyperLynx). - Previous involvement in volume production and high-reliability designs for data center or telecom applications.

Role Summary/Purpose: Hardware design engineer will closely work with worldwide engineers to perform engineering works for hardware testing solution of next generation semiconductor devices. The work includes requirement analysis, feasibility study, solution evaluation, task planning, project management, design execution, quality control and verification. We are working on cutting edge requirement and future technology. Responsibilities: • Provide global semiconductor interface test hardware solutions of next generation semiconductor devices for world-wide customers • Provide chip test interface HW solution engineering to compare pros and cons of different approaches and recommend best option to customers considering both performance, lead time, cost • Responsible for Testing circuits Design and super high layers PCB design for high complexity ATE device interface board correspond to various device testing, eg. Mobile application processor, High performance computer, AI, RF etc. • Responsible for scheme selection of a SUBSTRATE/MLO design in wafer testing, research for low Cost of Test scheme (considering TDE, Skip DIE, substrate stack-up) • Responsible for power integrity (PI) and signal integrity (SI) simulation at board level or system level, frequency domain or time domain to ensure HW product performance at design stage • Implement complex mechanical design/simulation, cable design, thermal evaluation by collaborating with PCB design to achieve premium quality in hardware solution according to customer device testing ultimate challenges. • Responsible for global end to end hardware project management to ensure best quality and on time delivery -Device testing requirement assessment and Feasibility study -Risk analysis and mitigation planning -Schedule planning and project management -Design execution -Regular review with global internal and external customers -Quality Control and Verification • Work closely with Global supply chain, provide solution to solve manufacture (DFM), assembly (DFA) challenges, ensure hardware products on time delivery and very high first pass rate • New technology research, new products, new materials evaluation for next generation device testing • Deliver hardware design training and seminars to customers

1. Be responsible for setting up and tuning the Linux system corresponding to EDA platform. 2. Be responsible for the daily maintenance of the servers, network equipment and related application components to ensure the reliable operation of the system. 3. Troubleshoot hardware and software errors by running diagnostics, documenting problems and resolutions, prioritizing problems, and assessing impact of issues. 4. Be responsible for collecting data from servers and systems and able to provide various reports based on this data to display operational status.

1. Project integration support & implementation, to deliver qualified nestlist from RTL. 2. preSTA/SYN/LEC/postSTA/etc. EDA flow execution and enhancement 3. Timing & power closure 4. Schedule control, netlist optimization, flow coordinator