「Sr. APR Engineer(竹北)」的相似工作

1. Be responsible for setting up and tuning the Linux system corresponding to EDA platform. 2. Be responsible for the daily maintenance of the servers, network equipment and related application components to ensure the reliable operation of the system. 3. Troubleshoot hardware and software errors by running diagnostics, documenting problems and resolutions, prioritizing problems, and assessing impact of issues. 4. Be responsible for collecting data from servers and systems and able to provide various reports based on this data to display operational status.

【主要工作內容】 1.Netlist to GDS, including floorplan/powerplan/physical synthesis/clock tree synthesis & routing 2.Chip level physical verification, including DRC/LVS/DFM & tapeout 3.IR-Drop analysis 【需求條件】 1.有使用過ICC/ICC2/laker, 曾做過fully layout & chip level PV 2.工作態度積極認真, 有獨自解決問題能力

DESCRIPTION: 1. Responsible for the physical design process of chip numbers from netlist to GDSII 2. Responsible for interaction with the front-end design team to realize the design convergence and optimization of the front and back ends; Comprehensive, static timing analysis 3. Floor planning, power planning and signoff, place and route, timing closure, chip static timing analysis and physical verification 4. IP integration, synthesis, verification and correction 5. Other Assigned Tasks delivered by the Line Manager QUALIFICATIONS: 1. MS degree in EE or related. 2. Familiar with physical design flow, including hierarchical design and low power design is a plus 3. Familiar with EDA tools, such as SoC Encounter/INNOVUS/ICC/ICC2 is a plus 4. Familiar with computer languages such as Perl/TCL/C-shell 5. Self-motivated with good communication skills and team spirit 6. Ability to understand and articulate technical issues. 7. Fluent English is a plus. 8. Experience in 12/5nm design is a plus.

RTL design/Verilog behavior model development APR flow support CAD/CAE internal flow/script maintenance

1. FrontEnd flow development. 2. Project support and consultant. 3. Develop CAD utility, design automation 4. Work with different process nodes, develop the design flow and methodology

* OSAT (Assembly/Test) 良率異常分析 & 處理。 量產測試驗證，確保量測參數 & 規格符合設計要求。 * 測試結果資料分析，提供良率改善 & 測試流程優化建議。 * CP / FT / SLT 數據追蹤，擬定調整製程參數 or 條件。 測試開發、Debug & 參數優化，提升測試效率 & 良率穩定度。 * 與內部製程/設備/品保單位進行問題分析，釐清異常並提出改善方案。 * 支援測試需求 & 技術交流，確保產品測試時程 & 品質達成量產目標。 1. Co-work w/ functional engineering team member (TME/DE/TD/TE/RE) to make new product has good definition, Risk evaluation and Build comprehensive testing plan / Qual plan, etc. 2. Co-work w/ other Engineering team member to ensure all new product can be thoroughly Manufactured, Characterized and Qualified for reliabilities and qualities. 3. Organize assignments and independently schedules to complete assigned tasks timely and make project finished efficiently. 4. Have good Coordination and Data Analysis to solve difficult problems through application of various techniques and approaches to develop effective and practical solutions that result in improved products, processes with good quality. 5. Co-work with MediaTek - Taiwan Team, and HCLTech - India Team. 6. Annual salary: 800K NTD and above 7. Onsite MediaTek - Hsinchu Science Park Office This position is set for PE (Product Engineer) to coordinate new product development activities, ensure timely completion of all new products manufacturing, testing, characterization, qualification and releasing with good consistency, quality and efficiency. Ref. * CP (Wafer level - Chip Probing) * FT (Packaged chip level - Final Test) * SLT (Packaged chip level - System Level Test) * ATE (Automated Test Equipment)

1. 熟練Autocad 電腦繪圖操作 2. 具備介面協調討論能力。 3. 其他主管交辦行政事項。

Key Responsibilities: 1. Design complex layout for mixed signal and analog circuit in CMOS technologies. 2. Work with circuit designers to floor plan and complete the layout. 3. Run and fix complete set of physical design verification and reliability verification. 4. Review and analyze the layout with the circuit designers. 5. Layout integration and final verification for tape out. Qualifications: 1. Experience in 28nm process node is preferable. 2. 3 years of relevant analog mixed signal or Serdes layout design experience. 3. Experience in whole chip layout floor planning & integration. 4. Experience working with most EDA tools like Virtuoso layout editor(IC618)、 Calibre DRC/LVS/XRC、Laker OA or L3. 5. Must have strong communication skills and be a team player.

1. 辦理股務相關作業及股務代理機構溝通窗口 2. 公開資訊觀測站重大訊息(中英文版)及各項公告申報 3. 協助安排董事會、功能性委員會、股東會及相關作業 4. 協助公司治理評鑑及相關作業執行 5. 永續資訊揭露、維護及優化: 彙編年報及股東會議事資料、永續報告書編製及查證作業 6. 其他主管交辦工作事項 1. Handle Employee stock option plan and stock affairs-related operations. 2. File material information and various announcements on the Market Observation Post System (MOPS). 3. Arrange and assist with shareholders’ meetings and other related meetings and tasks. 4. Assist in the implementation of corporate governance evaluations. 5. Disclose, maintain, and enhance sustainability information. 6. Support departmental operations and handle assignments from supervisors.

1.Analog & physical design flow/script development 2.IR/EM sign-off 3.Flip-chip design 4.Physical verification flow

【產品線描述】 高速傳輸 (USB4.0、DisplayPort、PCIe、HDMI) IC 【工作說明】 1. Analyze competitor and marketing trend. 2. Determine large scale, define project scope and objectives. 3. Engage of key customer’s project and business development. 4. Estimate the OEM’s RFQ to find the adequate applications & products. 5. New IC feasibility evaluation. 6. Develop/manage a detailed project progress and work plan in order to monitor the schedule on time/track/milestone achievement/areas for improvement. 7. Handle technical communications (FW design/USB roadmap/platform engagement) between RD & clients. 8. Coordinate the cross functional team for solutions of problems/issues when the product design in for qualification. 【必要條件】 1. Product and technical marketing relevant work experience. 2. Familiar with IC design flow and IC cost evaluation. 3. Excellent presentation and PPT design/preparation skill. 4. Outgoing and proactive personality. 5. Excellent verbal and written communication ability in both Mandarin and English.

• Co-work with package design team to complete a substrate layout that will meet the design objectives for performance, cost and quality. • Co-work with SOC team to complete Bump floorplan and RDL routing. • Power mesh/power density flow development and related flow development and enhancement. • Provide power plan result for PR team. • Chip IR signoff : provide the result and solution to APR & package team • Chip level PEM/SEM simulation and fixing plan providing. • SIR/DIR/PEM/SEM result data review and verification. • Familiar with Voltus / Redhawk experience is required.

1. 需具備類比IC Layout、BCD Prcoess整合經驗。 2. 需負責全晶片整合佈局和驗證 3. 熟悉Virtuoso, Laker, Calibre使用 4. 此職務上班地點在新竹辦公室

1. 專案規劃與管理 a. 專案前期評估 b. 規劃IC設計各個階段的schedule與人力配置，包括架構設計、RTL設計整合、合成、驗證和測試 c. 確保進度符合計劃，並有效利用團隊的資源來完成項目 d. 與外部供應商及客戶溝通，並與其他部門協作，確保IC設計能夠順利實現並符合最終需求 2. 技術監督與指導 a. 對設計整合流程進行技術監督，確保設計符合公司標準、品質要求，並能夠滿足性能、功耗、面積等要求 b. 確保設計整合的正確性，協調設計驗證過程，包括功能驗證、時序分析、功耗分析等 c. 協助團隊解決在設計整合與驗證時遇到的問題 d.負責 SOC low power 規劃及設計 e.熟悉並負責SOC IP( MIPI、DDR、PCIe 等) 的整合，確保與 SOC 設計的兼容性與效能最佳化 3. 團隊管理與領導 a. 負責指導部門內工程師，分配工作並提供技術指導，協助團隊克服技術挑戰 b. 招募新成員並確保團隊技能持續更新，推動專業發展和培訓計劃 c. 協調團隊內部的工作進度和溝通，確保各個成員的工作能夠高效協作 4. 其它主管交辦事項 【必要條件】 1. 電機、電子、資訊工程或相關科系，碩士以上學歷 2. 10年以上 SoC 設計或整合經驗 3. 熟悉CPU子系統設計整合 a. 熟悉 ARM 架構， b. 對 RISC-V 架構有基本認識 4. 熟悉數位IC前端設計流程，如RTL design、Lint/CDC、Synthesis、STA、LEC、ECO等 5. 熟悉 MIPI、DDR、PCIe、PHY、Serdes、PLL 等常用 IP 的應用與整合 6. 熟悉IC後段設計流程，如DFT、MBIST、P&R、post-cilicon system level debugging等 7. 良好的溝通能力，能與內部 RD 團隊及外包協力廠商有效協作，推動專案如期完成

請務必投遞官網(12475): https://careers.synopsys.com/job/hsinchu/applications-engineering-sr-staff-engineer/44408/85440860528 You Are: You are an innovative and resourceful engineer with a deep curiosity for solving complex technical challenges at the intersection of hardware and software. With a strong foundation in Electronic Engineering, Computer Science, or a related field, you are adept at leveraging your programming expertise—whether in Python, Tcl, Perl, or similar languages—to streamline and enhance engineering workflows. Your experience within UNIX/Linux environments equips you to navigate high-performance computing scenarios with ease. You thrive in collaborative, cross-functional teams and are energized by the opportunity to work closely with top-tier foundry partners and leading fabless companies. Your keen understanding of physical verification flows—such as DRC, LVS, PERC, FILL, and DFM—sets you apart, and you are eager to deepen your expertise in SoC physical design enablement, process effect analysis, and signoff. You are detail-oriented, capable of producing clear technical documentation, and communicate with clarity and empathy across diverse audiences. What You’ll Be Doing: 1.Delivering advanced physical verification solutions (DRC/LVS/PERC/Fill) for top-tier foundries and key fabless customers, ensuring high-quality silicon signoff. 2.Developing and validating process design kits (PDKs) and verification methodologies in collaboration with R&D and customer teams. 3.Partnering with R&D to innovate and improve Synopsys tools and flows, contributing to the evolution of physical verification technologies. 4.Providing hands-on customer support, troubleshooting issues, and delivering timely resolutions that enhance customer satisfaction and product adoption. 5.Coordinating with internal teams, including product managers and end-users, to align on best practices and ensure seamless integration of new technologies. 6.Documenting technical solutions, validation methods, and customer workflows for knowledge sharing and process improvement. 7.Staying up to date on industry trends and applying new insights to continuously optimize verification processes and tools. The Impact You Will Have: Accelerate the adoption and success of Synopsys physical verification products in leading-edge semiconductor manufacturing processes. Drive the development of robust PDKs and methodologies that enable customers to achieve first-time-right silicon. Enhance the quality and reliability of Synopsys verification tools through direct feedback and collaborative innovation with R&D teams. Strengthen Synopsys’ reputation as a trusted partner to top-tier foundries and fabless customers worldwide. Facilitate faster product cycles and reduced time-to-market for customers by delivering efficient and effective signoff solutions. What You’ll Need: BS or MS degree in Electronic Engineering, Computer Science, or a related field. Proficiency in at least one programming language, such as Python, Tcl, or Perl. Hands-on experience with UNIX/Linux environments and command-line tools. Familiarity with physical verification flows (DRC, LVS, PERC, FILL, DFM) and understanding of complex layout/electrical design rules. Strong investigative, analytical, and problem-solving abilities, with a passion for learning new technologies. Ability to produce clear, concise technical documentation and validation reports. Prior knowledge of tool/runset development/support and experience with SoC physical design is a plus.

Responsibilities - Execute performance validation plans on both emulator and silicon platforms. - Update and expand existing test cases based on instructions provided by senior colleagues. - Develop software for SoC validation Minimum Qualifications - Strong proficiency with the Linux command line, Git version control, and Gerrit code review process. - Solid experience in Embedded C programming; the ability to develop, debug, and maintain low-level or system-level code. - Familiarity with low-level software development concepts, including memory management and bitwise operations - Ability to accurately modify C source file parameters and logic according to established specifications. Preferred Qualifications - Familiarity with Mobile SoC Architecture, including key subsystems (e.g., CPU, ISP, TPU) and their data flow and communication mechanisms (e.g., interrupt, DMA). - Familiarity with using hardware/software co-verification tools such as the Zebu emulator and Verdi. - Knowledge of the Little Kernel or Android/Linux kernel concepts, and experience with Android GDB or other low-level debugging tools.

Your Job Molex is seeking a Senior PCB Layout Engineer to join our Optical Solutions Business Unit (OSBU). In this role, the successful candidate will be part of a world-class engineering team, contributing to the design and development of next-generation coherent and PAM4 optical transceivers. The Senior PCB Layout Engineer will be responsible for creating high-speed, high-density PCB layouts that meet stringent signal integrity, power integrity, and thermal requirements. This role involves close collaboration with electrical, mechanical, optics and process integration engineers across global teams to ensure optimal performance, manufacturability, and reliability of our advanced optical transceiver modules. Our Team R&D Optoelectronic Solutions What You Will Do - Lead multi-layer PCB layout design for high-speed optical transceivers (e.g., QSFP-DD, OSFP). - Translate complex schematics into production-ready layouts using EDA tools. - Define layout constraints, stack-ups, and component placement in collaboration with cross-functional teams. - Support board bring-up and debug through layout reviews, lab measurements, and issue resolution. - Ensure compliance with DFM, DFT, and IPC standards; coordinate with vendors to address fab and assembly issues. - Generate and manage all fabrication and assembly outputs (Gerbers, ODB++, BOMs, drawings). - Mentor junior engineers and drive continuous improvement in layout processes and design practices. Who You Are (Basic Qualifications) - Bachelor's degree in Electrical Engineering, Electronics Engineering, or a related field. - More than 8 years of hands-on PCB layout experience in high-speed digital or optical communication products. - Proficient in Allegro PCB design software. - Strong knowledge of high-speed signal integrity, power integrity, PCB stack-up design, and layout best practices. - Experience with interfaces such as SerDes (e.g., 112G/224G PAM4), I²C, SPI, MDIO, and power delivery networks. - Familiarity with EMI/EMC mitigation techniques and thermal design considerations. - Solid understanding of PCB fabrication and assembly processes. What Will Put You Ahead - Experience with 800G & 1.6T optical transceiver PCB layout. - Familiarity with signal and power integrity simulation tools (e.g., Sigrity, Ansys, HyperLynx). - Previous involvement in volume production and high-reliability designs for data center or telecom applications.

1.客訴分析處理與協助廠內改善跟催 2.處理客戶生產加工上所遭遇的問題, 解決並提供協助與對策 3.協助集團公司處理產品可靠度驗證與客訴問題 4.產品可靠度驗證暨產品可靠度監控 5.協助改善可靠度作業流程 6.HTOL/bHAST/PTC burn-in board規劃 7.ISO文件/表單制定及修改 8.其它主管交辦事項

Position Description: 1. To provide key technical support in digital IC design implementation, product demonstration, and sales presentations. 2. To demonstrate strong ability and to be hands-on in RTL-to-GDSII design methodology, including both challenging low power and high-performance designs. 3. Have real design experience including floorplan and partition, place, CTS, route, STA timing closure, Physical verification, RC extraction, Power Network analysis. 4. Assist in technical evaluation, assessment and delivery of concurrent ASIC/SoC designs. 5. To play a leading role among other team members, while receive little instruction on routine and general assignments. Position Requirements: 1. A bachelor's degree is essential and 3+ years’ experience in IC design, electronic engineering or computer science applications. 2. Ability to understand and articulate technical issues, (and knowledge of) design products and their applications. 3. Requires working knowledge of one or more programming languages, and effective communication and soft skills. 4. An MS degree and/or working experience in multi-nation IC design house/or familiar with EDI/Innovus product is a plus. 5. Good communication in English and good work attitude. 6. Be familiar with shell/Perl/Tcl etc. script language.

【職務內容】 1. 為客戶提供 ESD/surge 防護技術培訓，並指導客戶如何在各個端口設計適當的防護方案 2. 拜訪客戶進行溝通討論，並推薦合適產品及尋找新的應用專案 3. 針對客戶的實際測試需求，提供客戶可順利量產的 ESD/surge 防護整改方案 【需求條件】 - 電子電機相關科系畢業，無經驗者亦可(但須具備基礎電子學及電路學知識)，對於技術學習與挑戰充滿熱情。 【這裡的你】 我們需要的是具有熱情的問題解決者，能夠在面對技術挑戰時保持積極主動，並具備與客戶建立信任的溝通能力。如果你對電子技術有濃厚興趣，並希望在充滿挑戰的工作中持續成長，這就是屬於你的舞台！ #FAE工程師，挑戰技術的同時，掌握市場的脈動。來吧，加入我們，成為這個充滿機會與成就的職涯角色！