「數位IC工程師 (FPGA)(台北/新竹)」的相似工作

Overview We are seeking a highly skilled FPGA Engineer to architect and implement high-performance digital logic for next-generation camera platforms. This role is pivotal in enabling real-time video processing and efficient sensor integration. Key Responsibilities Design & Implement Camera Interfaces: Develop FPGA logic to handle high-speed camera data streams (e.g., MIPI, LVDS, CSI). Real-Time Image Processing: Integrate or design FPGA IP cores for image signal processing, filtering, and feature extraction. Sensor Synchronization: Ensure precise timing between multiple camera modules and other sensor inputs. Latency Optimization: Optimize FPGA architectures for low-latency video capture and data throughput. Verification & Testing: Create simulation testbenches and perform hardware-in-the-loop testing for camera pipelines. Collaboration: Work closely with camera hardware and system integration teams to define requirements and validate performance.

【工作內容】 • Work with team members and apply current functional verification techniques to perform and improve pre-silicon verification quality and product Time to Market • Provide the technical leadership to the DV team for the project • Work independently on various DV tasks and provide technical guidance to the DV team. • Be involved technically in the porting/creation of the DV environment for the new design, block and chip level test plan creation and implementation, coverage analysis, and regression cleanup 【職務條件】 • Master’s degree in Electrical Engineering, Computer Science, or related. • Good understanding of ASIC design verification flow. • RTL coding with Verilog/System Verilog and familiar with front-end design flow and C/C++ programming experiences. • Knowledge of Perl, OVL, SVA, SV, UVM, OVM, script programming, etc. 【其他條件】 • MSEE with a minimum of 5 years, or BSEE with a minimum of 8 years of experience in digital ASIC/SOC design verification • MS/BS degree in EE or CS with expertise in digital IP/SOC design verification.

制定全面的 x86 CPU 驗證計劃，確保驗證流程嚴謹且高效。 規劃並建立 UVM、 Constraint Random、Formal 驗證環境架構，提升驗證效率。 指導與培訓 Junior DV 團隊成員，確保驗證目標的順利達成。

1. 主動式電子掃描陣列 (相控陣列) 雷達系統之數位控制。 2. 熟悉Verilog與FPGA開發流程，了解High-Level Synthesis開發技術。 3. 具有實作數位訊號處理與數位架構設計於FPGA之經驗。

- 用Verilog/SystemVerilog撰寫RTL，負責數位電路介面與模擬驗證。 - 參與晶片模組整合與ASIC合成（含DFT、時序收斂）到Tape-out。 - 主導設計專案與SoC整合。 - 帶領小團隊（3人），負責任務分配與技術指導。

1. 支援計畫功能與系統驗證與除錯。 2. 規劃及協調驗證資源、項目及時程。 3. 與Hardware engineer 溝通設計FPGA硬體架構規劃 4. 與Software engineer 溝通設計FPGA 控制介面 5. SoC FPGA系統整合。 6. 演算法之RTL實現或IP整合、獨立撰寫 Testbench & Debug FPGA電路 7.高速介面(HDMI/eDP/3G-SDI/12G-SDI)、DDR、I2C、UART、SPI等介面整合應用 8. 具醫療影像及色彩處理開發

Job Description: Microchip’s Wireless Solutions Group is seeking a FPGA engineer to support SOC development for our next generation, mixed signal, wireless products. The role will focus on the areas of RTL design, FPGA synthesis and FPGA system bring-up, debug and validation. It will require a proactive candidate with a proven record of success in cross functional and cross site team environments. Key Responsibilities: • Collaborate with the design team to develop and optimize the RTL for FPGA , ensuring its efficiency and functionality. • Conduct FPGA synthesis using industry-standard tools to transform RTL code into a target FPGA device. • Assist in the initial bring-up of the FPGA system, ensuring proper functionality and identifying and resolving any issues that may arise. • Perform through testing and validation of the SOC design, both at the RTL level and in the FPGA implementation, and resolve any bugs or issues that are discovered. • Collaborate closely with the FW (Firmware), Validation, and RF teams to successfully carry out FPGA system bring-up, debug, and validation activities.

1. 熟Verilog及C/C++語言設計。 2. 規劃執行產品韌體之撰寫。 3. 執行、協助或配合韌體新技術之研發、導入。 4. 執行產品韌體測試。

The Staff/Sr. Engineer, CPLD will be based in Taiwan Taipei Wugu Site. The Staff/Sr. Engineer, CPLD performs the responsibility for CPLD programming and validation in Server/Storage Projects request. What a typical day looks like: 1. Skilled FPGA/CPLD Design Engineer with strong capabilities in Server/Storage system and hardware-level design. 2. Responsible for development and integration of CPLD/FPGA that implement functionality on prototypes: spanning from low-level hardware sequence control, logic control & status for embedded systems, to high-speed links, to high level IP blocks, to custom hardware-accelerated algorithms & filters. 3. Work closely with Hardware, BIOS, BMC and Firmware team for CPLD/FPGA development. 4. Designing validation plan and development spec. 5. Debugging platform and systems issues. The experience we are looking to add to our team: 1. 3-10 years of working experience in Firmware development. 2. Familiar in Verilog RTL language. Experienced with CPLD/FPGA development on Lattice, Altera and Xilinx devices. 3. Experience with I2C, SPI, LPC, UART, PCIe protocol design 4. Experience with verification methodologies, RTL and gate level simulations and debug. 5.Good problem-solving skills. The information we collect: We may collect personal information that you choose to submit to us through the Website or otherwise provide to us. This may include your contact details; information provided in online questionnaires, feedback forms, or applications for employment; and information you provide such as CV/Resume. We will use your information for legitimate business purposes such as responding to comments or queries or answering questions; progressing applications for employment; allowing you to choose to share web content with others or; where you represent one of our customers or suppliers, administering the business relationship with that customer or supplier.

1. IC產品之研發與應用設計 2. 建立IC產品基礎規格並設計IC電路 3. 降低產品成本，提高IC品質，支援軟/硬體開發 4. 熟數位IC設計及相關工具 Verilog HDL、Cadence IES simulator 、FPGA tools、Synopsys DC

Job Description: In this position the individual will develop test environment, test plan, and test cases based on the product specification and related industrial standards. The individual will require initiating a test plan review with the team and updating the test plan accordingly. The candidate will require executing and developing the test cases based on test plan, debugging and reporting the test result to achieve full function coverage goal. The individual will require developing ASIC bench functional test programs and doing ASIC bring-up and ASIC bench testing. The ideal individual must have proven ability to achieve results in a fast moving, dynamic environment. The candidate must have ability to coordinate priorities and initiatives and clear communication skill.

(1) FPGA軟硬體開發 (2) Verilog程式開發 (3) 軟硬體除錯

The successful candidate will work with team members and apply his/her design techniques to work on different phases of complex logic design for ASIC/SOC project. The role will include working on the following tasks from time to time: HDL coding, documentation, RTL quality check, cooperate with back-end engineer etc. 【Key Responsibilities】 - Responsible for front-end digital logic design in ASIC/SOC projects. - Perform HDL coding (Verilog/SystemVerilog). - Prepare and maintain design documentation (specifications and design documents). - Conduct RTL quality checks (Lint, CDC, power analysis, etc.). - Collaborate with Backend/Physical Design engineers to achieve timing closure. 【Core Requirements】 - Education/Experience: Master’s degree with ≥ 2 years, or Bachelor’s degree with ≥ 3 years of digital ASIC/SOC design experience. - RTL Design: Proficient in RTL coding using Verilog/SystemVerilog or VHDL. - TO / Front-End Flow: Familiar with front-end design flow, including synthesis, Lint, CDC, and STA. - EDA Tools: Experience with tools such as Lint, CDC check, and PrimeTime PX (power analysis). - Documentation: Ability to write design specifications and technical documents. - Collaboration: Work closely with the Design Verification (DV) team on IP verification. 【Preferred Qualifications】 - Familiarity with CPU architectures (x86/ARM/8051). - Knowledge of AMBA bus protocols (AXI/AHB/APB). - Understanding of PCIe protocol.digital IP/SOC design verification.

工作描述 - 跟據IP 需求制定硬件架構及硬件功能列表 - 跟架構、物理實現以及芯片驗證團隊一起合作去交付滿足功能/時序/功耗要求的設計，並協助流片前跟流片後的問題分析 - 交付SOC設計項目的RTL/SDC/UPF 設計 崗位要求 - 碩士以上，年資不限，電機、自動控制、電子、機械相關科系畢業為主 - 有好的溝通能力，能流暢的描述設計思想跟討論問題 - 有強烈的學習熱忱，對技術理論能有好奇心以及自趨力去成長

Familiar with digital IC design verification flow is a plus. Familiar with SV/UVM is a plus. Familiar with PCIE/NVMe is a plus. You will be in charge of making testplan according to the specification. You will take participate in creating verification testbench, test writing/debugging, and regression convergence. We focus on the storage related IP and prospective features. We provide high flexibility with days off and competitive salary.

We are seeking a highly motivated Design Verification Engineer to join our dynamic team. You will be responsible for ensuring the functional correctness of complex digital designs using industry-leading verification methodologies such as UVM, Formal Verification, and Coverage-Driven Verification. 【Key Responsibilities】 · Develop detailed verification plans based on design specifications and architectural documents. · Build and maintain System Verilog UVM-based testbenches for SoC/Subsystem/IP-level verification. · Write constrained-random and directed test cases to validate functionality, performance, and corner-case scenarios. · Perform coverage analysis (functional coverage, code coverage, assertions coverage) and drive towards coverage closure. · Apply Formal Verification techniques (e.g., property checking, connectivity checking) where applicable. · Support simulation regression runs and maintain automation scripts (Perl/Python/TCL/Makefile). · Participate in design and verification reviews, providing valuable feedback to improve quality.

Responsible for digital IP coding and micro-architecture design of low-power, high-performance LLM inference accelerators. Drive mapping of lightweight frameworks such as llama.cpp onto NPU, plan compute/memory subsystems, and optimize quantization & KV-cache for production-ready LLM SoCs. Write RTL specs and guide DV plans and P&R convergence for PPA targets. 1. 研讀規格。 2. IC數位邏輯線線路的研發設計。 3. IC數位邏輯線路模擬與合成。 4. FPGA的合成規劃與測試驗證。 5. IC的靜態時序分析 (Static Timing Analysis)。 6. IC佈局後的線路模擬。 7. 撰寫IC規格設計書。 8. IC的除錯與工程變更修改。 9. 協助系統應用部門的進行IC驗證版的規劃。

Job Description We are seeking a highly skilled ASIC Verification Engineer to join our team in Chupei, Taiwan. In this role, you will be responsible for developing and implementing comprehensive verification strategies for complex ASIC designs, ensuring the highest quality and reliability of our semiconductor products. Develop and execute verification plans for complex ASIC designs Create and maintain testbenches using SystemVerilog and UVM Design and implement efficient verification environments Perform functional and formal verification of digital designs Develop automated test scripts to improve verification efficiency Analyze and debug design issues identified during verification Collaborate with design engineers to resolve functional discrepancies Generate detailed verification reports and documentation Stay updated with industry trends and emerging verification methodologies Contribute to the continuous improvement of verification processes and tools Qualifications Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field 5+ years of experience in ASIC verification with strong proficiency in SystemVerilog and UVM Experience with Verilog, VHDL, and industry-standard simulation tools (e.g., Synopsys VCS, Cadence Xcelium) Experience of CPU, GPU, NPU or HBM verification Knowledge of formal verification techniques and tools Strong debugging, problem-solving, and analytical skills Solid understanding of digital logic design, computer architecture, and communication protocols Excellent organizational skills with strong attention to detail Good communication and teamwork skills in a fast-paced environment

我們正在尋找一位資深人員，帶領FPGA專案開發，包含主機板時序控制、客戶FPGA專案需求開發設計，及FPGA實作上必要時需與軟硬體研發團隊成員進行協作。 工作內容： 1. 數位邏輯設計並熟悉RTL Coding架構。 2. 熟悉並使用Altera Quartus或Xilinx Vivado開發FPGA系統。 3. 熟悉主機板CPU power sequence control。 4. 熟悉影像方面的高速介面(SDI/HDMI)、DDR高速介面、PCIe、I2C、UART、SPI等介面應用。 5. SoC FPGA系統整合。 6. FPGA IP 整合及驅動程式開發。

1.Integrated verification environment 2.Familiar with SoC level and IP level verification methodology 3.Develop verification plan and optimize verification flow 4.Familiar with verification methodology such as UVM, VMM, or OVM 5.Team player