「Senior Mixed Signal Design Engineer (SerDes, High Speed) - Taipei/Hsinchu」的相似工作

1.設計高速 SERDES 電路及相關Analop IP (TX,RX,PLL,I/O....) 2.熟悉以下電路尤佳 OSC, TX, DDR, Equalizer, PLL, DLL, CDR, Memory, Buck .

歡迎2026年畢業並正在找尋研發替代役的同學申請! 職位選擇: Direction 1: Mixed Signal Design Engineer Direction 2: Mixed Signal Analog Circuit Designer What you’ll be doing: • Develop and implement high speed interfaces and analog circuits. You will have hands on experience taking innovative integrated circuit designs at data rates of 25Gbps and higher from concept through silicon characterization. • Help by defining circuit requirements and complete design from schematic, layout, and verification to characterization. • Conduct schematic design of deep-submicron CMOS technologies using Spectre, Hspice or like. • Take ownership for the architecture, transistor design and verification using industry standard EDA tools such as Cadence virtuoso. • Optimize circuit to meet the specifications for system performance. • Work closely with layout engineers by providing detailed floorplan and guidance for matching and high-speed routings. • Provide support for post-silicon bring-up and debugging. What we need to see: • Hold a Master of Science/Ph.D in Electrical Engineering, Computer Engineering or related field with strong analog design background • CMOS Analog / Mixed Signal Circuit Design Experience in deep sub-micron process (especially in FINFET) • Experience with design and verification tools (Cadence's IC design environment, analog circuit simulation tools like Spectre, HSpice, Finesim, XA) • Experience in crafting test bench environments for component and top level circuit verification • Behavioral modeling of analog and digital circuits • Strong debugging and analytical skills • Analog simulation for noise analysis, loop stability analysis, ac/dc/tran analysis, monte-carlo, etc. • Strong interpersonal skills and ability & desire to work as a great teammate are huge plus. 應徵方式: 請提供以下資料： • 英文個人履歷 • 學士+碩士成績單 (中英文皆可) 提交申請: 請將上述資料投遞至104，符合資格者將會收到進一步的聯繫通知。

Job Description: As a team member of analog product business group, this role will support Analog IC circuit design of mixed-signal ICs, such as sensors, motor drivers, data converters. Key Responsibilities: 1. Co-work with talented design teams to develop high performance sensor related integrated circuits and products, such as Hall effect sensor, temperature sensor. 2. Contribute to chip architecture and circuit design decisions 3. Collaborate with validation, product engineering and test engineering teams to enable successful transfer to production 4. Also, will be responsible for circuit requirements definition, design, simulation and analysis, layout/test support, documentation and customer support for sensor applications. Qualifications: 1. Demonstrate strong analytical and problem-solving skills 2. Strong time management skills that enable on-time project delivery 3. In depth working experience with Cadence composer and Virtuoso, Spectre, HSpice and mixed-signal design flow. 4. Experience in lab measurement and equipment. 5. Self-starter. Passionate about creative work. Good communication skills and team player. Able to take the initiative and drive for results.

歡迎2026年畢業並正在找尋研發替代役的同學申請! What You'll Be Doing: • Post-layout model extraction for project review sign-off • pre-layout model extraction for DOE • Work closely w/ Package and PCB Design teams to design and ensure link performance meets expectation before tapeout • Develop novel algorithms & new methodologies to improve SI/PI/EMI modeling efforts • Work w/ Application Engineering teams to support customers w/ SI/PI questions • Support signal integrity simulation and analysis for interfaces PCIE, NVLink, display, LPDDR etc. What We Need To See: • MS in EE and majoring in SI/PI technology or equivalent experience, • Strong understanding of electromagnetics, specifically electromagnetic waves including transmission line theory and via properties, and the SI/PI/EMI applications; S/Y/Z parameters; discrete signal processing knowledge • Know how to use ANSYS HFSS/Q3D/SIwave/Designer, Synopsis HSPICE, Cadence PowerSI, and Keysight ADS • Understanding of high-volume manufacturing variations and impact to channel signal integrity is a plus • Familiarity with high-speed I/O design concepts including clock generation, transmitter & receiver design, and equalization schemes • Familiarity with transient simulation in tools and understanding of eye diagram methodology • Exposure to lab measurements including VNA & TDR, and oscilloscope experience • Passionate about SI/PI work Ways To Stand Out From The Crowd: • SI analysis flow including frequency and time domain simulation • PDN analysis flow including model generation and time domain simulation • PSIJ Analyses involving co-simulation of circuits and PDN models • Experience w/ Matlab, Python, VBS, and C • RF/microwave engineering; EMI/RFI analysis capability 應徵方式: 請提供以下資料： • 英文個人履歷 • 學士+碩士成績單 (中英文皆可) 提交申請: 請將上述資料投遞至104，符合資格者將會收到進一步的聯繫通知。

【成為円星人】 円星科技由一群專業與充滿熱情的夥伴創立於2011年，為積體電路矽智財設計服務業之新秀，秉持著『成為半導體業最值得信賴之IP公司』的願景，追求永續經營與成長。 誠摯歡迎您成為円星人，加入我們，站上國際舞台！ 一起共同打拚，以精品文化之精神，創造價值，追求卓越！ 【職務簡介】 M31主要業務為向 IC 設計業者和晶圓代工廠授權 IP，此職務為負責高速介面 IP（High Speed Interface IP）, 包含USB. PCIE 等SERDES IP設計工程師職缺。 【將負責的工作內容】 1. High-speed interface analog circuit design (TX, RX, etc) 2. Clocking related circuit design：PLL/CDR 3. Integrate mixed signal IP and handle co-simulation 【條件與特質】 1. 有類比IC設計工程師相關工作經歷5年以上 2. 電機電子/資訊工程碩士畢業 如果您有以上相關經驗且對此職缺有興趣，歡迎投遞您的履歷！

Are you an experienced IC design expert/architect with a passion for pushing the boundaries of technology? MediaTek, a leading semiconductor company, is currently seeking talented professionals to join our team! Work location: Hsinchu/Taipei/San Diego/San Jose

1. Responsible of preparing, coordinating and technical supporting Marvell SoC/ASIC projects using IPs developed by Marvell Central Engineering. 2. Preparation includes kick-off with BU and customer (if needed) about IP usage, risk assessment and IP/package/test board/test plan review, etc in pre-silicon phase as well as providing regular interlock and training to Marvell internal BUs. 3. Coordination includes driving the best engineering resources for SoC bring-up and issue debug until stable production is achieved. 4. Technical support is essentially using the knowledge and experience about Marvell PHY and supporting analog IPs to resolve any system and IP level issues observed from SoC bring-up to production. 5. The IPs are mostly Marvell multi-data rate high-speed SerDes as well as supporting analog IPs like analog bias, clock buffer and generator, process monitor, temperature sensor, etc. 6. The high-speed interface applications of interest are Ethernet single channel 10G/25G/50G/100G/200G KR/CR/C2M/C2C, PCIe Gen1-Gen6, CPRI, JESD, CEI, etc.

Synopsys is a leading company for SRAM IP solution. You will be in worldwide largest SRAM circuit/compiler design department. Build design with schematic concept, run simulation and verifications t o achieve a best SRAM compiler delivery. We'd like to see below knowledge from you. What you’ll be doing • SRAM IC design and robustness verification • SRAM compiler design, gds tiling, netlist tiling • Characterization of SRAM timing, power/…. • Compiler quality assurance Requirements: • Requires Master's degree in Electrical/Electronic Engineering or a related field • Prior understanding of CMOS based block level Circuit design, SRAM architectures understanding is plus • Understanding Digital Circuit Design and VLSI Process Concepts is desired • Strong desires to learn and explore new technologies concepts • Demonstrates good analysis and problem-solving skill • Basic understanding of Scripting language like python, tcltk, Perl, Unix shell • 1~4+ years of experience in SRAM circuit design. • SRAM bitcell analysis and design criteria development • SP/2P/ROM variety design experience • Post-silicon debug experience is a plus • EDA tool usage for simulations and design, XA/hspice/Verilog/Starrc/EMIR tools

Please apply this role through https://careers.synopsys.com/job/hsinchu/r-and-d-engineering-sr-staff-engineer/44408/84900058096 Synopsys is looking for motivated Product Engineer to help design, develop and test state of the art Static Timing, Characterization and Library modelling tools. The primary focus of the Product Engineer is closely working with R&D team, to influence technologies/solution roadmaps and provide R&D team with accurate input from Field AEs, helping them focus on the most critical design challenges and help define solutions to critical problems. The engineer will work closely with Field AEs, ensuring overall consistency of end-to-end design and analysis flow to meet customer needs. The engineer will also work with Sales and Marketing teams to find and develop new markets, drive new tool evaluations and help customers with the adoption and continuous usage of Static Timing, Characterization and Library Modelling, thus enabling Chip Design customers achieve best Timing, Power and Characterization Goals. Synopsys’ existing and forthcoming tools offer an advanced transistor-level static timing characterization and library modelling solution that addresses the existing and emerging challenges in custom and memory design. They offer predictability and improved productivity to designers. Their concurrent timing, SI features and advanced variation aware analysis enables designers to accurately and quickly identify design issues early-on and avoid expensive late-finding of problems in silicon. Main responsibilities: • Drive new products and new product features that exceed customer needs. • Work with RnD to enable timely implementation of new products and features, and important bug fixes. • Provide consultation to prospective users and/or product capability assessment and validation. • Provide tool trainings to customers and Field AEs. • Provides technical expertise to sales staff through sales presentations and product demonstrations. • Assists the sales staff in assessing potential application of company products to meet customer needs and preparing detailed product specifications for the development and implementation of customer applications/solutions. Requirements: We are looking for an innovative, motivated, and dependable person, with at least BS degree and 8+ years of recent hands-on experience including: · Exceptional expertise in transistor-level analysis and debug circuit level issues for SRAM, RF, ROM memories and Standard Cells. · Good exposure to static timing concepts and CMOS engineering fundamentals. · Good knowledge of TCL and or other scripting languages. · Very good communication, social and leadership skills. Plus: · NanoTime or PrimeLib experience highly desirable.

We are looking for a Mixed-Signal/Analog/IO Circuit Design Engineer – someone who is excited to join a rapidly growing team of creative circuit design engineers pushing frontiers of the high-speed SerDes solutions. NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can pursue, and that matter to the world. This is our life’s work, to amplify human creativity and intelligence. What you'll be doing: • Mixed-Signal/Analog circuit design for High-Speed I/O Interfaces • Develop and implement high speed interfaces and analog circuits using the latest CMOS FinFET processes • Help define circuit requirements and complete design from schematic, layout, and verification to characterization • Optimize design to meet the specifications for system performance. What we need to see: • TX/RX related design experience or is fairly familiar with high-speed SerDes/analog circuit design concepts • CMOS Analog / Mixed Signal Circuit Design Experience in deep sub-micron process (especially in FINFET) • Strong background of Cadence custom design tools, various circuit simulators like Hspice, XA, FineSim, Spectre • Experience in crafting test bench environments for component and top level circuit verification • Knowledge of Verilog, Verilog-A, Matlab, or similar tools for behavioral modeling of analog and digital circuits is a plus • Strong debugging and analytical skills • Strong interpersonal skills and ability & desire to work as a good teammate • Minimum bachelor's degree and/or pursuing Master's degree in Electrical Engineering.

Digital IC design engineer - Familiar with Verilog RTL coding - Familiar with digital design flow (pre-layout simulation, timing constraint, synthesis, post-layout simulation) - Will be working on high speed Serdes IPs - Experience or interest in all-digital PLLs or clock-data recovery circuits is a big plus

1.Design and maintain analog circuits 2.Survey and maintain design processes 3.Survey and maintain design tools and flow 4.Help training junior engineers 5.Debugging and measuring chip

【職位描述】 設計RVI公司新創的光通訊引擎(Optical Engine)類比電路設計工程師，負責設計、開發、測試、優化和調試類比電路及系統，產品矽中介層、玻璃中介層與高階基板。負責從概念到生產的電路設計，確保光引擎達到品質和性能標準。 【主要職責】 1.設計和開發創新的類比電路和系統，應用於光引擎和相關技術領域。 2.測試、優化和調試類比電路，確保其性能符合設計規範和功能需求。 3.與跨部門團隊合作，包括系統工程師、軟體工程師、光學工程師及其他專業人員，共同實現產品開發目標。 4.與客戶密切合作，理解其需求並提供技術支持和解決方案。 5.制定和執行測試計畫，分析測試數據，並提出改進建議。 6.保持對最新技術趨勢的了解，並將其應用於產品設計中以提升競爭力。 Position Description: As an Analog Circuit Design Engineer at RVI, you will be a key contributor to the development of our next-generation Optical Engine. You will be responsible for designing, developing, testing, optimizing, and debugging analog circuits and systems used in advanced optical communication modules, including silicon interposers, glass interposers, and high-end substrates. This role spans from initial concept to mass production, ensuring the performance and quality of the optical engine meet industry standards. Key Responsibilities: 1.Design and develop innovative analog circuits and systems for optical engines and related applications. 2.Test, optimize, and debug analog circuits to ensure performance meets design specifications and functional requirements. 3.Collaborate with cross-functional teams, including system engineers, software engineers, and optical engineers, to achieve product development goals. 4.Work closely with customers to understand their requirements and provide technical support and tailored solutions. 5.Develop and execute test plans, analyze test data, and propose design improvements. 6.Stay updated on emerging technologies and incorporate relevant advancements into circuit design to enhance product competitiveness.

******以下有兩個不同的職位****** 【Analog IC Designer (DRAM IO) - 竹北】 工作內容 1. IO 設計. 2. DDR RX/TX 設計. 3. DDR 類比. 4. 擁有 DRAM IO 設計經驗，有 DDR5 以上經驗者尤佳。 擅長工具: HSPICE、Python、Laker、ADP、Custom Compiler 1. 學習過電子學、電磁學、電路學、工程數學等基本課程且成績優良。 2. Familiar with Analog Circuit Design 【 Analog IC Designer (Integration) - 竹北】 工作內容 1. Analog IP top integration, including projects of SSD/UFS/eMMC/SD 等。 2. 基本類比電路設計概念，例如 LDO、DCDC、BANDGAP、Voltage Detector 或 PLL、ADC 等。 3. 協助故障樣品分析與 IC 測試。 其他條件 1. 熟悉量產相關知識與經驗者佳。 2. 類比設計經驗超過 3 年。

We are looking for a proactive and challenge-driven engineer to join our memory design team. This role primarily focuses on gate-level simulation and functional verification to ensure product quality and alignment with specifications. 【Key Responsibilities】 1. Memory circuit design and verification. 2. Gate-level verilog simulation against to the datasheet. 3. Failure mode analysis. 【Qualifications】 1. Experience in SRAM, DRAM, or other memory product design. 2. Solid understanding of digital circuit design and Verilog HDL. 3. Experience with simulation and debugging, able to work independently. 4. Hands-on experience in failure mode analysis is a plus. 5. Deep RTL design experience is not required, but strong gate-level simulation and verification skills are essential.

【成為円星人】 円星科技由一群專業與充滿熱情的夥伴創立於2011年，為積體電路矽智財設計服務業之新秀，秉持著『成為半導體業最值得信賴之IP公司』的願景，追求永續經營與成長。 誠摯歡迎您成為円星人，加入我們，站上國際舞台！ 一起共同打拚，以精品文化之精神，創造價值，追求卓越！ 【職務簡介】 M31主要業務為向 IC 設計業者和晶圓代工廠授權 IP，此職務為負責高速介面 IP（High Speed Interface IP）, 包含USB. PCIE, MIPI MPHY, CPHY, DPHY等SERDES IP和類比 IP（Analog IP）, 包含ADC, DAC, PLL, PVT sensor的類比IC設計工程師職缺。 【將負責的工作內容】 1. All-digital PLL, all-digital DLL : Clocking related solution 2. Digital assitantance calibration engine using in Serdes system 3. Integrate mixed signal IP and handle co-simulation 【條件與特質】 1. 混訊IC設計工程師相關工作經歷2年以上 2. 電機電子/資訊工程碩士畢業 如果您有以上相關經驗且對此職缺有興趣，歡迎投遞您的履歷！

*大學月薪33800元 / 碩士月薪38600元 1.申請與執行研究計畫。 2.負責報帳、經費申請、物品建檔等行政工作。 3.操作並維護計劃或實驗相關的設備與儀器。 4.協助資料收集和資料分析。 5.編輯、撰寫計畫報告書。

Job Description The successful candidate shall possess abundant experience in designing complex DSP for communication systems. She/he shall also have decent knowledge in analog/mixed-signal circuitry to perform the modeling and optimization of the overall high-performance front ends for communication SoCs. Imagine being part of a team that is fundamentally changing the way people communicate, the way they collaborate, the way they watch TV and explore the universe through the internet. Utilizing our uniquely differentiated technology, we have created an Intelligent Transport Network with more speed, capacity and scalability than ever before. Imagine a world with unlimited bandwidth. The network of tomorrow will allow for content and creativity limited only by the imaginations of its users. If this is something that interests you, that excites you, come take a look at a team not bound by large company obstacles and bureaucracy, where an idea today can be set in motion tomorrow. Come take a look at Infinera! Engaging in the design and implementation of the high-speed, highperformance analog / mixed-signal verifications, you have the chance to create the technical differentiation for Infinera to hold the market leadership. We together will revolutionize the era of efficient high-speed transmission. Essential Functions and Key Responsibilities: • Model the circuit blocks and mixed-signal IPs, including but not limited to high-speed ADCs, DACs, CTLE, FFE, and PLLs, to work with the architect and designers to achieve the optimal system-level performance. • Perform the functional verification and timing analysis on the IPs and the blocks. • Work with the digital verification team to generate the adequate interface to ensure the timing and connectivity. • Performs co-simulations on analog blocks and digital blocks in the mixed-signal simulation environment. Mandatory Knowledge/Skills/Abilities: • Has intimate knowledge of UVM verification flow. • Have prominent tracking record in modeling and verification of analog/mixed-signal IPs, including but limited to SERDES, optical links, and wireless transmission systems. • Hands-on in modeling and simulating with System-Verilog (WREAL), Verilog-AMS, and/or C, C++. • Have a decent understanding in CMOS analog / mixed signal design. Preferred Knowledge/Skill/Abilities: • Able to create IBIS-AMI model. • Can code in System-Verilog (WREAL). • Fluent in verbal and written communications. • Independently resolves issues and conquer design challenges. • Self-motivated and detail oriented. • Has good interpersonal skills. Education and Experience Requirements: • M.S. in E.E. with 8+ years’ experience, or Ph.D. in E.E. with 6+ years’ experience Additional Job Description: Infinera is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, religion, color, national origin, sex, age, status as a protected veteran, or status as a qualified individual with disability.

【產品說明】 TDDI顯示觸控整合產品 【工作內容】 1. Touch IC設計-類比AFE/ADC電路設計 2. 週邊電路設計 【必要條件】 研究所以上相關課系畢業. 熟悉類比電路設計,混合信號處理, 對類比電路設計充滿熱忱者.

請上傳英文履歷至官網(職缺代碼12427): https://careers.synopsys.com/job/hsinchu/r-and-d-engineering-sr-staff-engineer/44408/84643890752 You Are: You are a passionate and inventive engineer eager to advance the state of semiconductor technology. With a strong foundation in device physics, circuit simulation, and programming, you excel at translating complex technical challenges into innovative solutions. What You’ll Be Doing: 1.Researching, designing, and implementing advanced semiconductor component models, supporting both mainstream and emerging technologies. 2.Collaborating with peer R&D teams to integrate new technologies into SPICE/FastSPICE products, driving performance optimization. 3.Partnering with industry leaders to develop custom modeling and characterization methodologies tailored to cutting-edge applications. 4.Working closely with teams specializing in parasitic extraction, standard cell library characterization, and related domains to create comprehensive solutions for emerging technologies. 5.Providing expert-level technical support and guidance to key and strategic customers, ensuring their success with Synopsys products. 6.Driving innovation by contributing to the development of reliability modeling and advanced analysis features within SPICE/FastSPICE simulation tools. 7.Participating in cross-functional teams to ensure seamless product integration and a best-in-class user experience. The Impact You Will Have: Accelerate the adoption of next-generation semiconductor technologies through state-of-the-art modeling and simulation capabilities. Enhance the performance and reliability of SPICE/FastSPICE simulation products, directly influencing the success of global semiconductor leaders. Empower customers to innovate faster and with greater confidence by providing robust, accurate, and scalable simulation solutions. Shape the future direction of Synopsys’ EDA offerings by contributing to groundbreaking feature development and integration. Strengthen Synopsys’ reputation as a trusted partner and technology leader within the semiconductor industry. Drive industry standards for device modeling, reliability analysis, and advanced circuit simulation methodologies. Foster an inclusive and collaborative culture, mentoring junior engineers and promoting best practices across the organization. What You’ll Need: 1.MS or PhD in Electrical Engineering, Computer Science, Physics, Material Science, Applied Statistics, or Applied Mathematics, with 3+ years of relevant industry experience. 2.Strong knowledge of device physics, semiconductor process, and manufacturing flows. 3.Proficiency in programming with Linux, C/C++, and Python; solid foundation in data structures and algorithms. 4.Hands-on experience in SPICE circuit simulation or the development of related EDA software products. 5.Familiarity with Memory, Analog, Digital, High Frequency, or RF device/circuit design (a plus). 6.Experience or interest in machine learning applications and reliability analysis methodologies (a plus). Who You Are: Exceptional communicator, able to explain technical concepts clearly to diverse audiences. Strong problem-solver with a can-do attitude and resilience in the face of technical challenges. Team player who thrives in collaborative, multicultural environments. Self-motivated, organized, and able to manage multiple priorities effectively. The Team You’ll Be A Part Of: You’ll join a world-class R&D team at the forefront of SPICE/FastSPICE circuit simulation technology. The team is dedicated to developing, innovating, and implementing new technologies for device and reliability modeling, as well as advanced analysis features. Working closely with other market-leading product teams and industry partners, you will contribute to cross-functional projects that drive Synopsys’ leadership in EDA solutions. Our team values collaboration, knowledge-sharing, and a commitment to excellence in all aspects of product development and customer support.